))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
INSTRUCTOR'S MANUAL SOFTWARE AND HARDWARE ENGINEERING: MOTOROLA M68HC12
)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))Q
1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
COURSE ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
DETAILED COURSE PLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5
LABORATORY EXERCISES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MC68HC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MC68HC12 Program Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Addressing and Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hexadecimal and Binary Memory Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Binary Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Structured Assembly Language Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Structured Program Design and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Parallel Ports I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupts I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupts II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
SOLUTIONS TO CHAPTER PROBLEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1
1
INTRODUCTION
Software and Hardware Engineering: Motorola M68HC12, together with Microcontrollers and Microcomputers: Principles of Software and Hardware Engineering, is designed to give the student a fundamental understanding of microcontroller-based systems. The material is aimed at the sophomore, junior or senior level Electrical Engineering, Electrical Engineering Technology, Computer Engineering, or Computer Science student taking a first course in microcomputers. Prerequisites are a digital logic course and a first course in a programming language. This text is a successor to Software and Hardware Engineering: Motorola M68HC11 and, like that text, its overall objective is to provide an introduction to the architecture and design of hardware and software for the Motorola M68HC12. Although Software and Hardware Engineering: Motorola M68HC12 is designed to accompany a text explaining the general principles of software and hardware engineering, it can stand alone as a reference for M68HC12 users. It gives many programming and hardware interfacing examples that will enable students to become accomplished software and hardware designers. Of course, no one should expect to become an expert in using the M68HC12 in a single course. Two major members of M68HC12 family, the MC68HC812A4 and the MC68HC912B32, are described in detail. We also compare features of the M68HC12 with the M68HC12 for those students and engineers familiar with that microcontroller. In addition to covering the features common to all members of the M68HC12 family of microcontrollers, advanced features are discussed. These include the memory expansion capabilities of the MC68HC812A4 in Chapter 9 and the pulse-width modulator of the MC68HC912B32 in Chapter 10. The enhanced Serial Communications Interface (SCI) and Serial Peripheral Interface (SPI) are discussed in Chapter 11 and the analog-to-digital converter in Chapter 12. The fuzzy logic instruction set is covered in Chapter 13 with an example program showing a general-purpose inference engine. Chapter 14 describes the Background DebugTM module and other debugging features of the M68HC12 family. Chapter 15 describes advanced architectures of the M68HC12.
2
COURSE ORGANIZATION
The overall objective for this text and Microcomputers/Microcontrollers: Principles of Software and Hardware Engineering is to provide an introduction to the architecture and design of microcomputer/microcontroller hardware and software. We do not aim to make our students experts in using the M68HC12 microcontroller. The introductory chapter in Microcomputers/Microcontrollers: Principles of Software and Hardware Engineering explains the concepts of a stored program computer. A plausible design is created, and while the result doesn't answer all the questions students might have about how a computer is designed, nor is it very practical, it does give them a fundamental understanding about how a computer works. We want to dispel the mystery but we don't want to have too many details to obscure the relevant issues. The resources of the M68HC12 used in the laboratory are then explored with side trips to explain some important issues. Our goal is to be able to begin laboratory exercises while teaching other concepts. To do this, we introduce the basic hardware registers, the ALU, and the condition codes. The explanation of the condition codes register allows us to discuss binary codes and 2
coding. Even though students have learned about binary codes in their introductory logic courses, a review is beneficial. Special attention is paid to codes used for arithmetic and how the various codes affect the operation of the condition code register. By this time (at least in our course) the students are starting the concurrent laboratory and need to know how to program the computer. We point out that learning the instruction set of a processor involves knowing what the hardware resources are, what addressing modes have been implemented, and what general categories of instructions are available. A general discussion on addressing is provided with specific examples from the processor and instruction set being used in the laboratory. The mechanics of using an assembler are then presented in enough detail that the students can assemble and run small programs in the laboratory. The complete instruction set for the processor used is covered, at least in instruction categories. It is sufficient to lead the students through examples of using various instructions, particularly those with different addressing modes. By now the students are able to write, assemble, download, and run simple programs in the laboratory. Their experience will show the need for debugging tools. We discuss debugging tools in general in Microcomputers/Microcontrollers: Principles of Software and Hardware Engineering but the bulk of the information the students need is in Software and Hardware Engineering: Motorola M68HC12 where the debugging monitor supplied by Motorola with their EVB system is discussed. In courses where other debugging software or hardware is used, instructors can supplement this chapter with their own information. A large portion of the cost of developing any microcomputer system is the software. A key chapter in Microcomputer/Microcontroller Software and Hardware Engineering is dedicated to software design. The basic elements of software design are presented and the differences between design methodologies and design tools are discussed. Top down design is presented and pseudocode, probably the most widely used design tool, is promoted. This should reinforce software design concepts students receive in a previous course. The students are shown how to use structured programming principles in assembly language. The design of software modules, with attention paid to reducing interaction between modules, is also presented. Bus architectures and interfaces between external devices and a CPU are then discussed. Asynchronous bus transfer handshaking is covered. The basic input/output capabilities of the M68HC12 are discussed with laboratory exercises giving the students practical experience. After programmed input and output is covered, the need for interrupts and real time operations can be discussed. Various forms of interrupt processing are covered in chapter 8 of Microcomputer/Microcontroller Software and Hardware Engineering and the specific details necessary for the students to attempt interrupt processing on the M68HC12 in the laboratory are covered in chapter 8. By now the students understand the reason for memory (to store a program and data). We discuss the different types of memory, ROM and RAM, and why a system has both. Memory interfaces and timing signals are presented. Software and Hardware Engineering: Motorola M68HC12 chapter 9 shows the memory types available in the M68HC12. Many engineers have a terrible time with serial interfaces, especially the RS-232C "standard", because they don't understand why all the signals in the standard interface are there. One has to understand that the handshaking signals were developed for half-duplex communication channels. Once these concepts are understood, and that two different types of devices have the same name for different signals, the serial interface problem becomes much easier. Chapter 10 in Microcomputer/Microcontroller Software and Hardware Engineering provides complete coverage of serial interfaces. Interface cables for various RS-232C devices are shown and other 3
common interface standards such as RS-422, RS-423, and RS-485 are defined. The M68HC12 has two different types of serial interfaces. Each in covered in detail in chapter 11. The use of timers and the importance of real time events are then covered. The M68HC12 has an especially powerful timer section which students can use in their laboratories. I generally conclude my course with a discussion of the concepts of A/D conversion and its companion, D/A conversion. Chapter 11 in Microcomputer/Microcontroller Software and Hardware Engineering and chapter 12 in this text discuss and show examples of A/D conversion. Software and Hardware Engineering: Motorola M68HC12 includes chapters on fuzzy logic (chapter 13) and the powerful debugging features of the M68HC12 family (chapter 14 and Appendix A). I never get time to cover these but I hope you will.
3
DETAILED COURSE PLAN
The following detailed course plan shows how to closely integrate the two texts. In the reading assignments shown, "M" denotes Microcomputer/Microcontrollers: Principles of Software and Hardware Engineering, and "S" Software and Hardware Engineering: Motorola M68HC12. Lecture Number: 1 Topic: M68HC12 Instruction set Topic: Introduction and the picoprocessor Reading Assignment: S4 Reading Assignment: M1, M2.1-M2.3 Lecture Number: 10; 11 Topic: CASM Assembler Lecture Number: 2; 3 Topic: The picoprocessor Reading Assignment: S3, M5.1-M5.2 Reading Assignment: M2.4; M2.5-M2.8 Lecture Number: 12 Lecture Number: 3 Topic: Assembly language programming Reading Assignment: S6.1-S6.2, M4.5-M4.6 Topic: Registers and condition codes. Reading Assignment: S2.1-S2.3, M3.1-M3.2, MA.1 Lecture Number: 13 Topic: Debugging and testing. Lecture Number: 4 Reading Assignment: M5.9-5.10, S5 Topic: The condition code register. Reading Assignment: M3.5-M3.7 Lecture Number: 14 Topic: Code location. Lecture Number: 5 Reading Assignment: M5.3-M5.7 Topic: Memory architectures and addressing modes Lecture Number: 15 Reading Assignment: M4.1-M4.4 Topic: Top down design. Reading Assignment: M6.1-M6.7 Lecture Number: 6 Topic: Addressing modes with M68HC12 Lecture Number: 16 examples. Topic: Structured programming. Reading Assignment: M4.4, S2.6 Reading Assignment: M6.9 Lecture Number: 7; 8; 9
Lecture Number: 17; 18 4
Topic: Assembly language structured forms. Reading Assignment: S6.2
Topic: Interrupt service routines Reading Assignment: M8.8-M8.10
Lecture Number: 19 Topic: Module design. Reading Assignment: M6.12-M6.14
Lecture Number: 30 Topic: M68HC12 interrupt service routines Reading Assignment: S8.11
Lecture Number: 20 Topic: Introduction to parallel I/O Reading Assignment: M7.1-M7.2
Lecture Number: 31 Topic: Introduction to memory, RAM and ROM Reading Assignment: M9.9-M9.4
Lecture Number: 21 Topic: I/O timing and address decoding Reading Assignment: M7.3-M7.3
Lecture Number: 32 Topic: Memory timing diagrams Reading Assignment: M9.5-M9.6
Lecture Number: 22 Topic: M68HC12 I/O Reading Assignment: S7.1-7.5
Lecture Number: 33 Topic: M68HC12 memory Reading Assignment: S9.1-9.7
Lecture Number: 23 Topic: I/O handshaking Reading Assignment: M7.4, S7.8-7.9
Lecture Number: 34 Topic: M68HC12 timer Reading Assignment: S10.1-10.3
Lecture Number: 24 Topic: I/O synchronization Reading Assignment: M7.4, S7.8-7.9
Lecture Number: 35 Topic: M68HC12 timer interrupts Reading Assignment: S10.4-10.10
Lecture Number: 25 Topic: Simple I/O devices Reading Assignment: M7.6-M7.9
Lecture Number: 36; 37 Topic: Serial I/O Reading Assignment: M10.1-M10.9
Lecture Number: 26 Topic: Introduction to interrupts Reading Assignment: M8.1-M8.5
Lecture Number: 38 Topic: M68HC12 serial I/O Reading Assignment: S11.1-S11.4
Lecture Number: 27 Topic: Interrupt priorities and introduction to M68HC12 interrupts Reading Assignment: M8.6-M8.7, S8.1-S8.3
Lecture Number: 39 Topic: Analog I/O Reading Assignment: M11.1-11.7
Lecture Number: 28 Topic: M68HC12 parallel I/O interrupts Reading Assignment: S8.4-S8.7
Lecture Number: 40 Topic: M68HC12 analog-to-digital converter Reading Assignment: S12.1-S12.8
Lecture Number: 29 5
LABORATORY EXERCISES 5
Over the years a number of laboratory exercises have been developed. Here are a few, and you will find a growing collection of others for the M68HC12 and M68HC11 processors on the web at http://www.coe.montana.edu/ee/cady/books/profs.htm.
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MC68HC12 Introduction References:
Software and Hardware Engineering: Motorola M68HC12 chapter 5,
Pre-Lab:
Read Chapter 5: Debug-12 Monitor and Debugger
1.
LOOP
Using the Debug-12 Monitor, assemble the following program to be at $0800. (Note: Type a period <.> to get out of the ASM mode.) After it is in and you have checked that it is OK, run the program by typing G 800. Enter in ASM Whats in Memory Program Comment ASM 800 LDAB LDX JSR LDX JSR LDAA PSHA LDX JSR PULA DECA BNE SWI
': $FE04 0,X $FE02 0,X #5
Load ASCII code for : Load the vector for putchar Print what's in B on terminal Load the vector for getchar Get a new character in B Initialize loop counter Save the counter on stack $FE04 Load the vector for putchar 0,X Print it on terminal Retrieve the counter Decrement loop counter LOOP If counter <> 0, repeat Return to the monitor
LDAB LDX JSR LDX JSR LDAA PSHA LDX JSR PULA DECA BNE SWI <.>
#$3A $FE04 0,X $FE02 0,X #5
0800: 0802: 0805: 0807: 080a: 080c: 080e: $FE04 080f: 0,X 0812: 0814: 0815: $80e 0816: 0818:
c6 fe 15 FE 15 86 36 fe 15 32 43 26 3f
3a fe 04 00 FE 02 00 05 fe 04 00
f6
1.1 1.2 1.3
What does this program do? Change the ":" prompt to a "$". Change the loop counter so it prints exactly 15 of them.
2
Using elements of this program and other monitor utility routines, write, assemble and demonstrate a program which conforms to the following design: +)))))))))))))))))))))))))))))))))))), *Input character from the keyboard * .))))))))))))))))0)))))))))))))))))))+))))))))))2))))))))))))), *Add 1 to the character * .))))))))))0)))))))))))))+)))2))))))))), *Print +1= * .)))0)))))))))+))))))))))))))))))2)))))))))))))))))))))))), *Print the character to which 1 was added * .))))))))))))))))))0))))))))))))))))))))))))+))))2))))))))), *End program * .))))))))))))))-
Example. If you had entered the character A, the program display should show A+1=B. Demonstrate the program to your lab instructor.
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MC68HC12 Program Debugging 1
Pre-Lab:Read Chapter S-5.3.
2
Using the D-Bug12 Monitor, assemble the following program at $4000. After you have entered it, trace through it one step at a time. Explain to your lab instructor what you see on the screen. In particular, explain what is happening to the condition code register at each step. What’s in Memory Enter in ASM 4000 CE4000 LDX #$4000 4003 C602 LDAB #$02 4005 A600 LDAA 0,X 4007 08 INX 4008 53 DECB 4009 26FA BNE $4005 400B 3F SWI
3
Assemble the following program. The program is to allow you to enter a character from the keyboard and to print the hexadecimal code used by the computer to represent that character. For example, if you type A after starting the program the display should show A=41. It doesn't do it. Why not? Fix it so it does. Demonstrate to your lab instructor. Operation LDX $FE02 JSR PSHA LDAB LDX $FE04 JSR PULA LDX $FE18 JSR LDAB LDX $FE04 JSR LDAB JSR SWI
Operand Comment ; Get a character using getchar 0,X ; Save the character on the stack #$3C ; Load ASCII code for = ; Print it using putchar 0,X ; Get the character back from the stack ; Print its hex code using out2hex 0,X #$0D : Load ASCII code for carriage return ; and print it 0,X #$0A ; Load ASCII code for line feed 0,X ; and print it
4
Using elements of this program and other monitor utility routines, modify the program to print A = $41 or B = $42, etc. (including the spaces in front and back of the =).
5
Extra Credit: Modify the program so that it continues until the user types the Esc (escape) key..
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Addressing and CASM12 Introduction References:
Chapters 3 and 5 in Software and Hardware Engineering: M68HC12
1
Pre-Lab: Create a source file (ASCII text file) that reproduces your program from part 4 of Lab 2. Come to lab with this on your floppy disk. Read chapter S3 to see how to properly format this file for the CASM12 assembler.
2
Use the D-Bug12 Monitor ASM command to enter the following program at $4000. ldab ldab ldx ldab ldx ldab nop swi
#$10 $10 #$4000 7,x $4000 7,x
Demonstrate and explain to your lab instructor what is going on at each program step. You are to write a memo report explaining, for each line of code in (2), what addressing mode is employed and what the results were for each instruction. The memo is due next week. Use the Informative Memo Style (see the web page for an example of this type of report.) 3
Following the DOWNLOADING AN S19 FILE TO THE EVB instructions in the EE371 LABORATORY PROCEDURES handout, download the file lab3bug.s19 from the c:\ee371 directory. This program is to print out Good Job! five times on the screen (using the D-Bug printf monitor routine) and then quit. It doesn’t do it. You can see what it does by typing in G 4100 to run the program. Fix the program making use of breakpoints, tracing, and ASM.
4
Use the CASM12 cross-assembler to assemble the source program that you prepared as the pre-lab, upload it to the EVB and demonstrate it to your instructor.
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Addressing and Arithmetic 1
Pre-Lab: Come to the lab with a source file program prepared for the program specified in 2.
2
Create the following program
a.
Locate the program at $4000 using: PROG: EQU $4000 ORG PROG ... (Write your program op codes etc here) ... You are to set up 4 data buffers of 14 bytes each. Use the EQU, ORG, DB and DS assembler directives to initialize data in BUF1 and BUF2 and allocate storage for BUF3 and BUF4 as shown. Use the labels BUF1 - BUF4 and refer to them in your program.
b.
BUF1LOC: BUF2LOC: BUF3LOC: BUF4LOC: ORG BUF1: DB ORG BUF2: DB ORG BUF3: DS ORG BUF4: DS
c. d.
EQU $4100 EQU $4110 EQU $4120 EQU $4140 BUF1LOC $45,$45,$33,$37,$31,$20,$69,$73,$20,$66,$75,$6E,$21,$7F BUF2LOC $02,$2D,$32,$2A,$43,$00,$01,$FC,$42,$BA,$CC,$F5,$44,$01 BUF3LOC $0e BUF4LOC !14
The program is to: Add each bytes in BUF1 with the corresponding byte in BUF2 and store the result in BUF3. Exclusive-OR each byte in BUF3 with $20 and store the results in BUF4. Extra credit. After you have completed the program required for 2, add the capability to print out the contents of the four buffers in hexadecimal. Each of the four buffers should be printed like this, with a label (BUF1: etc) followed by the hex display of the 14 bytes in each buffer. BUF1:$45,$45,$33,$37,$31,$20,$69,$73,$20,$66,$75,$6E,$21,$7F BUF2:$02,$2D,$32,$2A,$43,$00,$01,$FC,$42,$BA,$CC,$F5,$44,$01 BUF3: ...(contents of BUF3)... BUF4: ...(contents of BUF4)...
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Hexadecimal and Binary Memory Display 1 2
3
Pre-Lab: Review Chapter S5.3 - Monitor Utility Routines. Come to the lab with a source file ready to do the following programming assignment. In the previous lab you programmed the M68HC12 to fill some data buffers and then to add and exclusive-OR the data. You are now to take that program and add the following features. a. Locate BUF1 and BUF2 contiguously in a constant data area in the EVB. That is, BUF1 should immediately follow the program code and BUF2 should immediately follow BUF1 in the EVB pseudo-ROM. To do this, eliminate the BUF1LOC and BUF2LOC equates and the associated ORGs. Locate BUF3 and BUF4 contiguously in the RAM data area in the EVB. BUF3 should be immediately followed by BUF4. To do this, equate BUF3LOC to $5000 and delete the BUF4LOC equate and ORG. b. Initialize all data locations in BUF3 and BUF4 to zero each time the program is run. Be prepared to demonstrate that you are doing this. c. Do the arithmetic and exclusive-OR just as you did in the last Lab. d. Output the string "BUF1:" followed by the bytes in BUF1 as hex values, i.e., if memory contains 01000101 01000101 ..., the display should be BUF1: 45 45 ... (note the space between the values). You must print all data values from BUF1 e. Output a carriage return, line feed to the screen. f. Output the string "BUF2:" followed by the bytes in BUF2 to the screen just like in 24. Do the same for BUF3 and BUF4. g. Output another carriage return, line feed. h. Output the string "The binary values in BUF4 are:" followed by a carriage return, line feed. i. Output the first 5 bytes in BUF4 in the format $Hex_Value = %Binary_Value $Hex_Value = %Binary_Value ... Where Hex_Value is the hexadecimal display of the data in BUF4 and Binary_Value is a binary display. Each of the five data locations should be on a separate line. A typical output would look like this: BUF1: 45 45 33 37 31 20 69 73 20 66 75 6E 21 7F BUF2: 02 2D 32 2A 43 00 01 FC 42 BA CC F5 44 01 BUF3: 47 72 65 61 74 20 6A 6F 62 20 41 63 65 80 BUF4: 67 52 45 41 54 00 4A 4F 42 00 61 43 45 A0 The binary values in BUF4 are: $67 = %01100111 (First byte in BUF4) $52 = %01010010 (Second byte in BUF4) $45 = %01000101 (etc) ... Extra Credit. Assume the code for the numbers in BUF4 is unsigned binary. Add the following printout to the program. 11
The decimal values in BUF4 are: $67 = 103 $52 = 82 $45 = 69
12
Binary Arithmetic 1
This program will be similar to the previous lab where you will add together each memory location in BUF1 with the corresponding location in BUF2 and save the result in BUF3. There is no BUF4. Each buffer is 1310 bytes long and contains the following data:
BUF1: DB BUF2: DB
$FF,$FF,$01,$70,$7F,$80,$80,$81,$C0,$C0,$FF,$00,$01 $01,$02,$01,$0D,$01,$01,$80,$81,$C0,$BF,$FE,$FE,$FE
BUF1 and BUF2 are to be located in the pseudo-ROM and BUF3 is to be located in the data ram area of the EVB. For each addition, your program is to print out the two data values being added and the sum. If as a result of the addition an unsigned binary overflow occurs, print out the message Unsigned overflow occurred. If as a result of the addition a two's complement overflow occurred, print out the message Two's-complement overflow occurred. If both types of overflow occur, both message should be printed. For example, when adding the first two bytes, you should display: $FF + $01 = $00 Unsigned overflow occurred Each addition should be printed on a new line. (Hint: You will have to save the condition code register after the addition so you can print the error messages. There are a couple of ways to do this. You can push and pull it or you can use the transfer register instruction TFR C,A and TFR A,C to transfer into and out of the A register.) 2
Extra credit: Add two additional lines printed out for each addition that show the equivalent addition in decimal assuming first, unsigned binary code, and second two'scomplement binary code. For example, the printout for the first addition would show: $FF + $01 = $00 Unsigned overflow occurred 255 + 1 = 0 Unsigned addition -1 + 1 = 0 Two's-complement addition
13
Structured Assembly Language Programming 1
Pre-Lab: Review Chapter S6.2 - Structured Assembly Language Programming. Come to the lab with a source file ready to do basically the same program that you did for Lab 5 EXCEPT: You are to write STRUCTURED ASSEMBLY LANGUAGE CODE to implement the following design. You MUST implement this design and you MUST use structured code. You may use subroutines as needed or wanted. You may add more design comments and other comments if you wish but you may not change the design in any substantial way. A source file with the following pseudo code design comments is as follows:
; Pseudo code design ; Initialize counter1 to number of bytes ; DO (add and XOR the bytes in the bufs) ; Get value from BUF1 ; Add value from BUF2 ; Store sum in BUF3 ; XOR sum ; Store in BUF4 ; ENDO ; WHILE (Counter1 != 0) ; Output "BUF1: " ; Output BUF1's data and CR, LF ; Output "BUF2: " ; Output BUF2's data and CR, LF ; Output "BUF3: " ; Output BUF3's data and CR, LF ; Output "BUF4: " ; Output BUF4's data and CR, LF ; Output "The binary values in BUF4 are:"
; Output CR, LF ; Initialize Counter1=5 ; DO (Output 5 bytes in hex and binary) ; Get data from BUF4 ; Output $ and the hex data value ; Output " = %" ; Initialize Counter2=8 ; DO (Output the binary value) ; IF MSB of data = 1 ; THEN Print "1" ; ELSE Print "0" ; Shift data left ; ENDO ; WHILE (Counter2 != 0) ; Output CR, LF ; ENDO ; WHILE (Counter1 != 0) ; Return to monitor
14
Structured Program Design and Implementation 1. Pre-Lab: Do a top down design for the program specified below. You and your lab partner are to work together to produce a fully structured design using structured programming and pseudocode. The design must have at least one WHILE-DO or DO-WHILE and at least one IFTHEN-ELSE. You should carry the design to a level where you can easily convert the design to a program. This design is to be a file and each line is to be used as a comment in your program. Show your design to the lab instructor BEFORE you start coding the problem. 2. Implement the design using structured assembly language code. Write an assembly language program using ONLY structured code. The Program Prompt the user to enter a character. Use a prompt that is informative and tells the user what you want. After the user has entered the character, print it out in the following format: (Assume the user has typed the z key.) The character you entered was: z Its ASCII code is: Hexadecimal: $7A (Print the hex representation for the character the user typed.) Binary: %01111010 (Binary representation for the character.) Continue the above until the user types the ESC character. When the ESC character is printed, instead of printing out the information shown above, the program must display the following: The character you entered was: We now return you to your regularly scheduled program. and then return to the B-Bug12 monitor. You are to use a subroutine to print out the binary code. The byte to be printed will be input to the subroutine in the A register. The subroutine must not alter any registers including the condition code register. Nothing is returned to the calling program.
15
Parallel Ports I/O 1
The I/O board attached to the EVB has a set of 8-switches attached to Port J and 8-LEDs attached to Port H. You may read from the switches by loading from Port J and write to the LEDs by storing to Port H. LED Display: The LEDs are attached to port H through a 74LS373 octal latch with tri-state output. Port H is used for the 8-bit output (and a zero written to the port turns the LED on). Port F, bit6 must be asserted high to latch the data. The tri-state output is permanently enabled. I suggest you write a subroutine to enable the LEDs using the following design: ; Set the data direction register DDRH so all bits on Port H are output ; Set bit-6 in data direction register DDRF so bit-6 is an output ; Assert bit-6 in Port F high to allow the LED output latch to follow ; the data on Port H. To display data on the LED, you must first complement the byte to display and then output to Port H. Write a subroutine to do that. Switch Port: The switches are input to Port J through a 74LS244 octal tri-state buffer. At reset, Port J will be configured as an input but it is a good idea to initialize it to be an input anyway. Port S bit-2 is used for the output enable and must be asserted low when reading from the switches. I suggest you write a subroutine to enable the switch port using the following design: ; Set the data direction register DDRJ so all bits on Port J are input ; Set bit-2 in data direction register DDRS so bit-2 is an output. To input data from the switch, Write a subroutine to assert Port S bit-2 low to enable the buffer, read the data from Port J and then deassert Port S bit-2. (You may need a short delay (NOP) after asserting bit-2 and before reading the data.) Here are the equates for the registers you will be using. See chapter S7 (page 202, 205206) for more information PORTH: EQU $0024 DDRH: EQU $0025 PORTF: EQU $0030 DDRF: EQU $0032 PORTS: EQU $00D6 DDRS: EQU $00D7 PORTJ: EQU $0028
2
Write an assembly language program to do the following: ; Initialize all I/O ; DO ; Input a value from the switches ; IF the value is different from the last one displayed ; THEN ; Display the value on the LEDs ; Print carriage return, line feed ; Print "The switches are set to: $xx (where xx is the 2 digit hex value) 16
; ENDDO ; WHILE the switches are not set to %00000000 ; Print carriage return, line feed
17
Interrupts I
1
Enter the IRQEX2.ASM program shown below and demonstrate that it works. Because the IRQ input is asserted when the signal is low (the switch pressed), the test program should print out the message continuously when the switch is pressed.
2
Modify IRQEX2.ASM so that the message is printed out once and only once each time the switch is pressed. Hint: You will need to change only one line of code in IRQEX2.ASM to do this.
3
Port J-7 is connected to the SDB switch on the I/O board. Write an assembly language interrupt program that uses the key wakeup feature of Port J. Refer to S233-S242 for information. The program is to perform to the following specifications: Foreground Job: When an interrupt is not being serviced, your foreground job is to continuously get a characters from the keyboard and then display them on the screen. It should do this forever or until the RESET switch is pressed (whichever comes first). Background Job: The background job, or interrupt service routine, is to be entered when the SDB switch is pressed. Every time the switch is pressed the following message is to be printed on the display: carriage-return linefeed SDB switch pressed carriage-return linefeed A requirement of the routine is that this message is to be printed once, and only once, each time the SDB switch is pressed. The message is to be printed when the switch is pressed, not when it is released.
18
; Sample listing to initialize interrupt vectors ; in a system WITH a Dbug-12 Monitor ; irqex2.asm ; EE371 Fall 1999 ; Memory map equates ROM: EQU $4000 RAM: EQU $6000 STACK: EQU $8000 ; IRQ system equates INTCR: EQU $1e ; Interrupt control reg IRQEN: EQU %01000000 ; IRQ enable bit ; D-bug12 monitor equates SetVec: EQU $fe1a Printf: EQU $fe06 IRQNUM: EQU !25 ; IRQ num for SetVect ; org ROM lds #STACK ; Initialize rest of machine including ; any interrupt system details. ; Initialize the D-Bug12 monitor interrupt vector ldd #IRQISR ; Get adr of ISR pshd ; Stack for SetVec ldd #IRQNUM ; Get the number jsr [SetVec,pcr] puld ; Clean up stack ; Enable the IRQ interrupt bset INTCR,IRQEN ; Unmask interrupts cli ; The main process is a loop which runs ; forever. ; DO loop: ; yada, yada, yada ; WHILE (forever) bra loop ;*************************************** ; Here are the interrupt service routines IRQISR: ; blah, blah, blah, whatever ; Print a test message ldd #irqmes jsr [printf,pcr] rti ; Special return ;*************************************** irqmes: DB "External IRQ detected " DB 0d,0a,00 .nolist
19
Interrupts II 1
It is my fervant and lasting hope that you will actually do a structured design for the following program. If you do you will get it done much faster than if you don't.
2
Write a program that has a foreground job that does no processing other than to monitor the Port J, bit-0 toggle switch to see if a rocket launch is to proceed. When the switch input is one, the foreground job is to allow the countdown for launching a rocket. The countdown is to be produced by an interrupt service routine described in (a) below. If the Port J-0 switch is changed to zero, the countdown sequence is to hold at its present count and then resume when the switch is changed back to one. After the countdown reaches Blast Off! as described in (a), return to the D-Bug12 monitor. If the SDB switch (Port J, bit-7) is pressed at any time, the launch is to be aborted and control returned to the D-Bug12 monitor as described in (b).
There are to be two interrupt service routines. a.
Using the timer overflow flag to generate 1 second timing intervals, write an interrupt service routine that prints out the launch countdown from 10 to 0. The countdown is to be printed on the screen and should decrement every second (or as close to a second as you can get). Each digit is to be on a new line. When zero is reached, the display is to show Blast Off! instead of zero. (Note that the countdown is to start only after the user sets the bit-0 switch to one. Once the countdown starts, it continues until it reaches Blast Off! unless Port J-0 is zero putting the countdown into a hold or the user presses the SDB switch.)
b.
Port J-7 is connected to the SDB switch on the I/O board. Write an interrupt service routine that uses the key wakeup feature of Port J so that when the switch is pressed the launch sequence is aborted and the message **** LAUNCH ABORTED **** is printed on the screen. After this, control is to be returned to the D-Bug12 monitor. You must not return to the monitor directly from the interrupt routine. You must return to the foreground job and then exit.
20
3
SOLUTIONS TO CHAPTER PROBLEMS
SOLUTIONS TO CHAPTER 2 PROBLEMS 2.1 2.2 2.3
Which of the M68HC12 ports is used for the A/D converter inputs? Port E Which of the M68HC12 ports is used with serial I/O? Port S Draw the programmer's model for the M68HC12. +))))))))))))))0)))))))))))))), *7 A 0* 7 B 0 * .))))))))))))))2))))))))))))))-
or +))))))))))))))))))))))))))))), D 0 * *15 .)))))))))))))))))))))))))))))+))))))))))))))))))))))))))))), *15 X 0 * .)))))))))))))))))))))))))))))+))))))))))))))))))))))))))))), *15 Y 0 * .)))))))))))))))))))))))))))))+))))))))))))))))))))))))))))), *15 S 0 * .)))))))))))))))))))))))))))))-
2.4
2.5
2.6
Which bits in the M68HC12 condition code register may be tested with conditional branching instructions? The negative, zero, two's-complement overflow and carry bits may be tested by conditional branch instructions. Calculate the effective address for each of the following examples of indexed addressing. a. X = $5000 LDAA 0,X EA = $5000 b. Y = $5000 STAA $10,Y EA = $5010 c. X = $500D LDAA $25,X EA = $5032 Describe the following M68HC12 addressing modes: Immediate, Direct, Extended, Indexed, Indexed-in direct, Inherent, Relative Immediate: The data for the instruction immediately follows the op code. Immediate addressing is used for constants known at the time the program is assembled. Direct: Direct addressing uses an 8-bit address to directly access a location in the first 256 bytes of memory. Extended: Extended addressing uses a 16-bit address to access a memory location anywhere in the 64 Kbyte address space. Indexed: Indexed addressing generates the effective address by adding a 8-bit, straightbinary offset (specified by the instruction) to the contents of the IX or IY registers. 21
2.7
2.8
2.9
2.10
A 16-bit address is the result. Indexed-Indirect: This mode uses indexed addressing to find the address of the memory location which contains the address of the data. Inherent: Inherent addressing means the instruction itself specifies where the operand is located. Relative: Relative addressing is used for branch instructions. An 8-bit, two'scomplement offset specified by the instruction is added to the contents of the program counter. Discuss the relative advantages and disadvantages of direct and extended addressing. Direct addressing uses only 8 bits to specify the address of the memory data and thus is faster and uses less memory than extended addressing. Its disadvantage is that only 256 memory locations can be addressed. Extended addressing requires 3 bytes for the instruction and address and thus takes longer to execute and requires more memory. Extended addressing can access the whole 64 Kbyte address space. Discuss the relative advantages and disadvantages of extended and indexed addressing. Indexed addressing can be a two byte instruction. Thus it is faster and uses less memory than extended addressing. Its major advantage is that the address of the data can be determined at run-time and the index register can be incremented and decremented to step through tables of data. What is in the following CPU registers after a system reset? A, B, CCR, Stack Pointer A, B = unknown. In the CCR, the I, X and S bits are set and the rest of the bits are unknown. The stack pointer is unknown. Discuss how the CPU fetches the first operation code of the first instruction to be executed following a system reset. After the system reset, the CPU fetches the address of the first op code to be executed from $FFFE:$FFFF.
SOLUTIONS TO CHAPTER 3 PROBLEMS 3.1
3.2 3.3
Give four ways to specify each of the following constants. a. The ASCII character X. 'X', "X", $58, !88, %01011000, Q01011000 b. The ASCII character x. 'x', "x", $78, !120, %01111000,Q01111000 c. 10010 !100, $64, %01100100, Q01100100 d. 6416 !100, $64, %01100100, Q01100100 Give the symbol used when specifying a constant in the following bases: hexadecimal - $, decimal - !, binary - %, ASCII - ' ' or " " What assembler pseudo-operation is used to allocate memory for data variables? DS
22
3.4 3.5
What assembler pseudo-operation is used to define strings of ASCII characters? DB What assembler pseudo-operation is used to define byte constants in ROM memory? DB What assembler pseudo-operation is used to set the assembler's location counter? ORG How are data storage areas located when using the CASM assembler? By using ORG pseudo-operations Your hardware designer tells you that the microcontroller will have ROM located at addresses $E000 to $FFFF and RAM at $0800 to $0FFF. Show how to inform the assembler so that it locates its code and data areas properly. ORG $E000 The program and constant definitions follow this. ORG $0800 The variable data allocations follow this. Give the addressing mode and the effective address for each of the following instructions:
3.6 3.7 3.8
3.9
LDAA #5
Mode Immediate
LDAA $5 LDAA $5,X STAA $081A
Direct Indexed Extended
Effective Address The contents of the program counter after the opcode has been fetched $0005 The contents of the X register plus 5 $081A
SOLUTIONS TO CHAPTER 4 PROBLEMS 4.1
You be the assembler. Assemble the following source code just as the CASM12 assembler would do it.
cprb1ans.asm 0000 0000 0000 0000 F000 F000 F002 F004 F007 0800 0800
4.2 4.3
8607 8B0A 7A0800 3F
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11
COUNT: MAX: ROM: RAM:
DATA
EQU EQU EQU EQU ORG ldaa adda staa swi ORG DS
04/09/1998
21:12
PAGE 1
!7 !10 $F000 $0800 ROM #COUNT #MAX DATA RAM 1
In the program above, what addressing mode is used for the ldaa instruction? Immediate In the program above, what addressing mode is used for the staa instruction? Extended
23
4.4 4.5
What is in memory location $0800 before the program runs? Unknown. The DS reserves a memory byte. It does not initialize it. For each of the following questions, assume the memory display of the M68HC12 shows: 5000
B0 53 05 2B 36 89 00 FF FE 80 91 3E 77 AB 8F 7F
Give the results after each of the following instructions are executed. a. LDAA $5000 A = $B0, NZVC = 100b. Assume X = $5000 LDAA
c.
0,X
LDAA
4.6
d.
PSHX PULD LDD $5000 LDX $5002 XGDX
e.
Assume X = $5000
c. d.
4.9
A = $00, NZVC = 010-
X = $2B36, A = $2B,
B = $36
D = $052B, X = $B053
$0A,X
D = $913E
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. SP = $5005 b.
4.8
6,X
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. LDX $5000 X = $B053 b. LDY $5002 Y = $052B c. LDX $5003
LDD
4.7
A = $B0, NZVC = 100-
Assume X = $5000
PULA SP = $5005 PULA PULB SP = $5005 PSHA PSHB SP = $500A PULA PSHB
A = $89,
SP = $5006
A = $89 B = $00
SP = $5003
A = $91,
SP = $500A
Why do store instructions not use the immediate addressing mode? The data for an immediate instruction immediately follows the opcode and programs are usually stored in ROM. Therefore, one cannot store data in ROM at run-time. Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. Assume X = $5000 BSET
b.
6,X,$AA
EA = $5006, (EA) = $AA
Assume X = $5007 BCLR
d.
($5000) = $BF
Assume X = $5000 BSET
c.
0,X,$0F
0,X,$AA
($5007) = $55
Assume Y = $5000 24
BCLR
4.10
4.11
4.12
b. c. d.
LDAB ABA LDX LDAB LEAX LDAB ADDB
e. f.
$5004 A = $61, B = $36, NZVC = 0000 $5000 $5007 B,X $5009 $500A
X = $B152, NZVC = ---B = $11, NZVC = 0011
9,X $0A,X
A = $11, NZVC = 0011
Assume X = $5000 LDAA SUBA LDAA LDAB ABA ADCA
9,X $0A,X $5000 $5001 $5002
A = $EF, NZVC = 1001
A = $09, NZVC = 0000
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. LDAA $5006 b. c. d. e.
4.14
($5000) = $00
Assume X = $5000 LDAA ADDA
4.13
0,Y,$FF
Assume A = $C9 and the NZVC bits are 1001. Give the result in A and the NZVC bits for each of the following instructions. a. LSLA A = $92, NZVC = 1001 b. LSRA A = $64, NZVC = 0011 c. ASLA A = $92, NZVC = 1001 d. ASRA A = $E4, NZVC = 1001 e. ROLA A = $93, NZVC = 1001 f. RORA A = $E4, NZVC = 1001 The ASLx instructions have the same operation codes as the LSLx instructions. Why? Both shift a 0 into the least significant bit and shift the most significant bit into the carry bit. Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. LDAA $5003
NEGA LDAA $5007 NEGA NEG $5009 LDAA $5006 COMA LDAA $5007 COMA COM $5009
A = $00, NZVC = 0100 A = $01, NZVC = 0001 ($5009) = $80, NZVC = 1011 A = $FF, NZVC = 1001 A = $00, NZVC = 0101
f. ($5009) = $7F, NZVC = 0001 After an addition, the carry bit in a status register indicates that a 2's complement overflow has occurred - false.
25
4.15
4.16
The following straight binary addition was done in the M68HC12. What is the binary result and what are the N, Z, V, and C flags? 01010111 01100110 10111101 N=1, Z=0, V=1, C=0 Assume the following M68HC12 code is executed in sequence. Give the hexadecimal result in each of the registers after each instruction is executed. ldaa ldab aba adca
4.17
#$4A #$D3 #$70
c. d.
$5002 $5004
ORAA LDAA EORA LDAA ANDA LDAB COMB
V 0 0 0 1
C 1 0
A = $2F, NZVC = 000A = $2E, NZVC = 000A = $8B, NZVC = 100B = $FA, NZVC = 1001
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. LDAA $5000 A = $B0, NZVC = 0010 b. NZVC = 0100 c. NZVC = 1000 Assume A = $00 and memory location DATA = $B0. A CMPA DATA
$5001 $5006 $5007
instruction is executed followed by a conditional branch. For each of the conditional branch instructions in the table, indicate by yes or no if you expect the branch to be taken. BGE yes BHS no
4.21
Z 0 0 0 0
A = $3B A = $41
$5003 $5002 $5003 $500D $500E $5002
CMPA TST TST
4.20
N 0 0 0 1
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. a. LDAA $5002 b.
4.19
B xxxx D3__ D3__ D3__
Use the contents of memory shown in problem 4.5 and give the results of the following instructions. LDAA ADDA DAA
4.18
A 4A__ 4A__ 1D__ 8E__
BLE no BLS yes
BGT yes BHI no
BLT no BLO yes
BEQ no
BNE yes
Assume A = $05 and memory location DATA = $22. A CMPA DATA instruction is executed followed by a conditional branch. For each of the conditional branch instructions in the table, indicate by yes or no if you expect the branch to be taken. BGE no BHS no
BLE yes BLS yes
BGT no BHI no
BLT yes BLO yes
BEQ no
BNE yes
26
4.22
Assume A = $56 and memory location DATA = $22. A CMPA DATA instruction is executed followed by a conditional branch. For each of the conditional branch instructions in the table, indicate by yes or no if you expect the branch to be taken. BGE yes BHS yes
4.23
4.25
BGT yes BHI yes
BLT no BLO no
BEQ no
BNE yes
Assume A = $22 and memory location DATA = $22. A CMPA DATA instruction is executed followed by a conditional branch. For each of the conditional branch instructions in the table, indicate by yes or no if you expect the branch to be taken. BGE yes BHS yes
4.24
BLE no BLS no
BLE yes BLS yes
BGT no BHI no
BLT no BLO no
BEQ yes
BNE no
Briefly describe what each of the following instructions do. These are separate instructions, not a program. COMA 1's Complement the A register CBA Compare A to B = (A)-(B) and set flags CMPB 10,X Compare B to memory (B)-(M) where the address of memory is 10 plus the contents of the X register TSTB Test the B register for zero; modifies the N and Z flags BRN Branch never SWI Software interrupt. Used as a breakpoint in the EVB monitor BITA $80 Tests if the A register is $80; modifies N and Z and resets V BCC LOOP Branch carry clear to LOOP; take the branch if C=0, otherwise continue with the next instruction XGDX Exchange the D register with X LSR $5000 Logical shift right the contents of memory location $5000 NEGB Two's-complement the B register Draw a memory map showing the contents of the stack expected after the program in Example 4-13 is executed. What value do you expect in the A register after the subroutine adds all the data? 9F4: 9F5: 9F6: 9F7: 9F8: 9F9:
08 14 0A 09 08 07
Return Address Data " " "
9FA: 06 9FB: 9FC: 9FD: 9FE: 9FF:
Data 05 04 03 02 01
" " " " "
A = $37
SOLUTIONS TO CHAPTER 5 PROBLEMS 5.1
You downloaded an S-record file to the EVB and the D-Bug12 Monitor responds with the message "Invalid Command". What went wrong? 27
5.2
5.3
You probably forgot to start the download with the LOAD command. What sequence of keystrokes would you use to put the hexadecimal data 11, 22, 33, 44 into memory locations $5000-$5003? MM 500011223344. Write a short D-Bug12 assembler (ASM) code segment showing how to use the DBug12 Monitor utility routine putchar to print the letter A on the terminal. ldab ldx jsr swi
5.4
Write a short CASM12 code segment showing how to use the D-Bug12 Monitor utility routine putchar to print a $ on the terminal. putchar:
5.5
EQU ldab ldx jsr swi
5.8
EQU EQU DB ldd ldx jsr swi
5.10 5.11 5.12 5.13
$FE06 0 "Hello World",NULL #MESG printf 0,x
How does the D-Bug12 monitor know when to stop printing characters in the printf routine? The printf routine prints characters until it finds a null ($00) character. Write a short D-Bug12 assembler (ASM) code segment showing how to use the DBug12 Monitor utility routine out4hex assuming the data to be printed is at $5000. ldd ldx jsr swi
5.9
#$5000 $FE06 0,x
Write a short CASM12 code segment showing how to use the D-Bug12 Monitor utility routine printf. printf: NULL: MESG:
5.7
$FE04 #'$' ; Load ASCII code for $ putchar 0,x
Write a short D-Bug12 assembler (ASM) code segment showing how to use the DBug12 Monitor utility routine printf to print a null-terminated string starting at $5000. ldd ldx jsr swi
5.6
#$41 $FE04 0,x
$5000 $FE18 0,x
What command is used to set a breakpoint at $4016? BR 4016 What command is used to clear all breakpoints? NOBR What command is used to display what breakpoints are currently set? BR What command is used to set register A to $AA? A AA What command is used to display memory locations $5000 to $502F MD 5000 5020
28
SOLUTIONS TO CHAPTER 6 PROBLEMS 6.1
For each of the logic statements, give the appropriate M68HC12 code to set the condition code register and to branch to the ELSE part of an IF-THEN-ELSE. Assume P and Q are 8-bit, unsigned numbers in memory locations P and Q. a. ; IF P >= Q
b.
c.
6.2
P Q ELSE_PART Q P ELSE_PART P Q ELSE_PART
For each of the logic statements, give the appropriate M68HC12 code to set the condition code register and to branch to the ELSE part of an IF-THEN-ELSE. Assume P and Q are 8-bit, signed numbers in memory locations P and Q. a. ; IF P >= Q
b.
c.
6.3
ldaa cmpa blo ; IF Q > P ldaa cmpa bls ; IF P = Q ldaa cmpa bne
ldaa cmpa blt ; IF Q > P ldaa cmpa ble ; IF P = Q ldaa cmpa bne
P Q ELSE_PART Q P ELSE_PART P Q ELSE_PART
For each of the logic statements, give the appropriate M68HC12 code to set the condition code register and to branch to the ELSE part of an IF-THEN-ELSE. Assume P, Q and R are 8-bit, signed numbers in memory locations P, Q and R. a. ; IF P + Q >= 1
b.
c.
ldaa P adda Q cmpa #1 blt ELSE_PART ; IF Q > P - R ldaa Q adda R cmpa P ; Q + R > P? ble ELSE_PART ; IF (P > R ) OR (Q < R) ldaa P cmpa R bgt THEN_PART ldaa Q cmpa R bge ELSE_PART
29
d.
6.4
; IF (P > R) AND (Q < R) ldaa P cmpa R ble ELSE_PART ldaa Q cmpa R bge ELSE_PART
Write M68HC12 assembly language code for the following pseudocode design assuming K1, K2, and K3 are 8-bit, signed or unsigned, numbers in memory locations K1, K2, and K3. Assume memory has been allocated for these data.
s6-4ansc.asm
0000 B6001C 0003 810D 0005 2715
0007 B6001D 000A B1001E 000D 2608
000F 72001C 0012 73001D 0015 2003
0017 73001C
001A 20E4
001C 001D 001E
6.5
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
12/08/1998
21:14
PAGE 1
; WHILE K1 does not equal $0d while_start: ldaa K1 cmpa #$0d beq end_while ; DO ; IF K2 = K3 ldaa K2 cmpa K3 bne else_part ; THEN ; K1 = K1 + 1 inc K1 ; K2 = K2 - 1 dec K2 bra end_if ; ELSE else_part: ; K1 = K1 -1 dec K1 ; ENDIF K2 = K3 end_if: ; ENDO ; ENDOWHILE bra while_start end_while: ; Data variables K1: DS K2: DS K3: DS
1 1 1
Write a section of M68HC12 code to implement the design given below where K1 and K2 are unsigned 8-bit numbers in memory locations K1 and K2.
s6-5ansc.asm
0000 B60012 0003 B10013 0006 2405 0008 7A0013 000B 2005
000D 8664 000F 7A0012
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11
; IF K1 < K2 ldaa K1 cmpa K2 bhs Else_Part ; THEN K2=K1 staa K2 bra Endif ; ELSE K1=64 Else_Part: ldaa #!64 staa K1
30
05/24/1998
02:14
PAGE 1
12 13 14 15
0012 0013
6.6
Write a section of M68HC12 code to implement the design given below where K1, K2 and K3 are signed 8-bit integer numbers stored at memory locations K1, K2 and K3.
s6-6ansc.asm
0000 B60023 0003 B10024 0006 2C1B
0008 B60025 000B B10024 000E 2F08 0010 B60023 0013 7A0024 0016 2006
0018 B60025 001B 7A0024
001E 720023 0021 20DD
0023 0024 0025
Endif: ; ENDIF K1 < K2 K1: DS 1 K2: DS 1
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
; WHILE K1 < K2 While_Start: ldaa cmpa bge ; DO ; IF K3 > K2 ldaa cmpa ble ; THEN K2 = K1 ldaa staa bra ; ELSE K2 = K3 Else_Part: ldaa staa End_If: ; ENDIF K3 > K2 ; K1 = K1 + 1 inc ; ENDO bra
05/24/1998
02:16
PAGE 1
K1 K2 End_While
K3 K2 Else_Part K1 K2 End_If
K3 K2
K1 While_Start
End_While: ; ENDWHILE K1 < K2 ; Data allocation K1: DS 1 K2: DS 1 K3: DS 1
6.7
For problem 6.6, assume K1=1, K2=3 and K3= -2. How many times should the code pass through the loop and what are the final values of K1, K2 and K3? One pass through the loop; final values are K1=2, K2= -2, and K3= -2;
6.8
Write structured M68HC12 code for the following design: IF A1 = B1 THEN WHILE C1 < D1 DO Decrement D1 A1 = 2 * A1 ENDO ENDWHILE C1 < D1 ELSE A1 = 2 * B1 ENDIF A1 = B1
Assume that A1, B1, C1, and D1 are 16-bit unsigned-binary numbers and that memory 31
has been allocated in the program by the following code: A1: B1: C1: D1:
DS DS DS DS
2 2 2 2
Assume A1, B1, C1 and D1 are initialized to some value in some other part of the program. s6-8ansc.asm
0000 FC002D 0003 BC002F 0006 261C
0008 FC0031 000B BC0033 000E 2412
0010 FE0033 0013 09 0014 7E0033 0017 FC002D 001A F3002D 001D 7C002D
0020 20E6 0022 2009
0024 FC002F 0027 F3002F 002A 7C002D
002D 002F 0031 0033
6.9 6.10
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
05/24/1998
02:19
PAGE 1
; IF A1 = B1 ldd A1 cpd B1 bne else_part ; THEN ; WHILE C1 < D1 while_start: ldd C1 cpd D1 bhs end_while ; DO ; Decrement D1 ldx D1 dex stx D1 ; A1 = 2 * A1 ldd A1 addd A1 ; Double it std A1 ; ENDO ; ENDWHILE C1 < D1 bra while_start end_while: bra end_if ; ELSE else_part: ; A1 = 2 * B1 ldd B1 addd B1 std A1 ; ENDIF A1 = B1 end_if: A1: DS 2 B1: DS 2 C1: DS 2 D1: DS 2
For problem 6.8, assume A=2, B=2, C=3, and D=6. What final values do you expect after the code has been executed? A=16, B=2, C=3, D=3. For the program in Example 6-11, how does the assembler evaluate the expression DATA2-DATA1. What is it's value. Why does one use an expression here instead of just putting in a defined (equated) constant value? DATA2-DATA1 = 4. You use an expression to let the assembler calculate the size of the buffer. That way, if the number of bytes in DATA1 changes, the program automatically changes when it is reassembled.
32
6.11
6.12
6.13
6.14
6.15
6.16
6.17
For the program in Example 6-11, what is printed on the screen when the program is executed? STAa carriage-return, line-feed. Why are JSR instructions used to branch to the D-Bug12 Monitor subroutines rather than BSR instructions? BSR instructions are relative addressing and the monitor subroutines are more than 127 bytes away. So a JSR instruction that uses extended addressing must be used. For the program in Example 6-12, how many bytes are reserved for "data" in the RAM. How many bytes of stack are used by the program? NUMCHR+3 = 6. The program uses two bytes of the stack each time it jumps to a monitor subroutine plus whatever the routine uses. How does the D-Bug12 Monitor know when to stop printing characters in the printf routines? An NULL character ($00) signifies the end of the string to be printed. Write a routine using the putchar() monitor subroutine to output characters to the terminal. Assume the register X points to the start of the string to be output and the string is terminated by the ASCII EOT character. Write a routine that outputs the character in A. The routine is to check for unprintable ASCII characters (codes $00-$1F, $7F-$FF). If one of these characters occurs, print the "#" character. A 16-bit number is in sequential memory positions DATA1 and DATA1+1 with the most significant byte in DATA1. Write an M68HC12 code segment to store the negative of this 16-bit number in DATA2 and DATA2+1.
SOLUTIONS TO CHAPTER 7 PROBLEMS 7.1
7.2
7.3
7.4
7.5
What levels must be on the BKGD, MODA and MODB pins at & R& E& S& E& T to place the M68HC12 into normal-expanded mode? (1 0 1) Into normal single-chip mode? (1 0 0) Give the data register addresses for Port A, B, C, H, and J. PORTA = $0000, PORTB = $0001, PORTC = $0004, PORTH = $0024, PORTJ = $0028 How do you control the direction of the bidirectional bits in the M68HC12 I/O ports. Each of the bidirectional data ports has a data direction register. Writing a one to a bit in the DDR enables that bit to be an output. Design an output circuit with 8 LEDs connected to Port B. The LEDs are to be on when bits in a byte stored in location DATA1 are 1's. Show the hardware and software required. Design an input circuit to input the states of eight switches to the M68HC12.
33
SOLUTIONS TO CHAPTER 8 PROBLEMS 8.1 8.2 8.3 8.4
8.5 8.6 8.7 8.8 8.9
When the I bit in the condition code register is set to 1, interrupts are: B. disabled. Interrupts are masked when you get to the interrupt service routine - true. In the M68HC12 interrupt service routine, you MUST unmask interrupts with the CLI instruction before returning - false. How are interrupts unmasked if the CLI instruction is not executed in the interrupt service routine? When the condition code register is pulled from the stack by the RTI instruction, the I bit is cleared. How many bytes are pushed onto the stack when the M68HC12 processes an interrupt request? 9 Which instruction is used to globally unmask interrupts? CLI Which instruction is used to globally mask interrupts? SEI What address does the M68HC12 use to find the address of your interrupt service routine for a timer overflow? $FFDE:FFDF Assume a dedicated application system (no D-Bug12 Monitor) with ROM at $E000$FFFF and RAM at $0800 - $0BFF. Show how to initialize the interrupt vectors for the & I& R& Q and Timer Channel 1 interrupts. Assume IRQISR and TC1ISR are labels on the respective interrupt service routines.
prb8_9c.asm
0000 0000 0000 E000 E000 A7 E001 0B E002 A7 E003 0B FFEC FFEC E000 FFF2 FFF2 E002
8.10
Assembled with CASM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
; TC1ISR:
EQU EQU EQU
$FFEC $FFF2 $E000
ORG
PROG
21:45
PAGE 1
; TC1 Vector location ; IRQ Vector location ; Program location
nop rti
; TC1 ISR
; IRQISR:
nop rti ; Locate the vectors ORG TC1VEC DW TC1ISR ORG IRQVEC DW IRQISR
; IRQ ISR
Repeat problem 8.9 but assume your code is to be run on a system with a D-Bug12 Monitor. Show the code that is necessary to vector the M68HC12 to the correct interrupt service routines.
prb8_10c.asm 0000 0000 0000 0000 0000
TC1VEC: IRQVEC: PROG: ;
01/25/1998
Assembled with CASM 1 2 3 4 5
TC1NUM: IRQNUM: SetVec: PROG: STACK:
EQU EQU EQU EQU EQU
!22 !25 $FE1A $0800 $0A00
34
12/08/1998 ; ; ; ; ;
23:38
PAGE 1
User Vector Number for TC1 User Vector Number for IRQ D-Bug12 SetUserVector Program location Stack location
0800 0800 CF0A00
0803 0806 0807 080A
CC081C 3B CC0016 15FBF60C
080E 0811 0812 0815 0819
CC081E 3B CC0019 15FBF601 1B84
081B 3F 081C A7 081D 0B 081E A7 081F 0B
8.11
8.12
8.13
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
; ORG lds
PROG #STACK
; ; Initialize the vector for TC1 ldd #TC1ISR ; Get the address of the ISR pshd ; Put on the stack ldd #TC1NUM jsr [SetVec,pcr] ; Initialize the vector for IRQ ldd #IRQISR ; Get the address of the ISR pshd ; Put on the stack ldd #IRQNUM jsr [SetVec,pcr] leas 4,sp ; Clean up stack ; - - swi TC1ISR: nop ; TC1 ISR rti ; IRQISR: nop ; IRQ ISR rti
For the interrupt service routine in Example 8-10, where would you put a breakpoint to find out if you are getting to the interrupt service routine. Set a breakpoint at the first instruction in the ISR. Assume you have written a program similar to Example 8-10 where the bell is to beep whenever you assert Port H, bit-0. When you run the program, instead of beeping once, the bell beeps continuously, much to the annoyance of your lab partners and supervisor. What has gone wrong? The programmer has not reset the key wakeup flag properly in the interrupt service routine. Write a complete M68HC12 program in assembly language for an interrupt occurring on the external IRQ source. The interrupt vector is to be at $FFF2:FFF3. When the interrupt occurs the ISR is to increment an 8-bit memory location "COUNT" starting from $00. The foreground job is to be a spin loop "SPIN BRA SPIN". Assume: 1. The D-Bug12 monitor is not installed. 2. Code is to be located in ROM at $E000. 3. RAM is available between $0800 and $0BFF
prb8_13c.asm 0000 0000 0000 0000 0000 0000 0800 0800 01 E000 E000 CF0A00
Assembled with CASM 1 2 3 4 5 6 7 8 9 10 11 12 13
01/25/1998
PROG: EQU $E000 ; STACK: EQU $0A00 ; RAM: EQU $0800 ; IRQVEC: EQU $FFF2 ; IRQEN: EQU %01000000 INTCR: EQU $1e ; ; Allocate Data Area ORG RAM Count: DB 1 ; ORG PROG lds #STACK ; ; Initialize memory counter
35
21:50
PAGE 1
Program Location Stack Location RAM Location IRQ Vector Location ; IRQ Enable Bit Interrupt Control Register
Initialize stack pointer = 0
E003 790800 E006 4C1E40 E009 10EF E00B 20FE
E00D 720800 E010 0B FFF2 FFF2 E00D
8.14 8.15
8.16
8.17
8.18
8.19
8.20
8.21
14 15 16 17 18 19 20 21 22 23 24 25 26 27
clr Count ; Enable the IRQ interrupt bset INTCR,IRQEN ; Unmask interrupts cli ; Foreground job is a spin loop spin: bra spin ; ; Interrupt Service Routine ISR: inc Count ; No overflow detection rti ; Initialize the vector for IRQ ORG IRQVEC DW ISR
What is the priority order of interrupts in the M68HC12. See the list of interrupt vector assignments in Table 8-4. How can the priority order of interrupts be changed? The HPRIO register contains eight bits which can allow any of the interrupt sources to be promoted to the top of the hierarchical order. The priority can only be changed when the interrupts are masked (I-bit = 1). The Timer Channel 3 interrupt and the Real Time Interrupt happen to occur simultaneously. Which is serviced first? The Real Time Interrupt is service first unless the Timer Channel 3 has been promoted to the highest position by reprogramming the HPRIO register. What is the SWI instruction and what does it do? SWI is a software interrupt instruction. It is a single byte and CPU treats it as if an interrupt has occurred. All registers are pushed onto the stack and the processor fetches a vector from $FFF6:FFF7. What instructions can be used to reduce power consumption when waiting for an interrupt to occur? WAI and STOP. Define interrupt latency. Interrupt latency is the time delay between the interrupt request and when the interrupt service routine is entered. What are the components of interrupt latency? Interrupt latency is comprised of the following: 1) The time to complete executing the current instruction. 2) The time to push the registers onto the stack. 3) The time to fetch the vector and transfer to the interrupt service routine. In addition, if the processor is in another ISR with interrupts masked, the latency is increased by the time required to complete the ISR and unmask the interrupts. Show how to modify the code in Example 8-4 to have the ISR service all interrupts generated by any of the four key wakeup bits.
; Interrupt Service routine ISR: ; Service all interrupts that have been generated. ; Check each one in turn ldaa KWIFJ ; Get the flags ; IF bit-0
36
bita #BIT0 beq Chk_1 ; THEN DO the bit-0 ISR ; ... ; IF bit-1 Chk_1: ldaa KWIFJ ; Get the flags bita #BIT1 beq Chk_2 ; THEN DO the bit-1 ISR ; ... ; IF bit-2 Chk_2: ldaa KWIFJ ; Get the flags bita #BIT2 beq Chk_3 ; THEN DO the bit-2 ISR ; ... ; IF bit-3 Chk_3: ldaa KWIFJ ; Get the flags bita #BIT3 beq Done ; THEN DO the bit-3 ISR ; ... ; Done: ; Now reset all flags that have been set ldaa KWIFJ staa KWIFJ rti ; Return to interrupted prog
SOLUTIONS TO CHAPTER 9 PROBLEMS 9.1
9.2 9.3
9.4
9.5 9.6
On reset, the RAM in the MC68HC812A4 is mapped to $0800 and the 512 byte register block to $0000. The locations of these can be changed. Describe how this is done. The INITRM ($0010) and INITRG ($0011) can be programmed with the most significant byte of the new address. This can be done only once in your program. What registers are used to remap the data RAM, EEPROM, and control registers? The INITRM ($0010), INITEE ($0012) and INITRG ($0011) registers. What is the default memory location of EEPROM in the MC68HC812A4? $1000-$1FFF in expanded mode systems and $F000-$FFFF in single-chip systems. What is the default memory location of the Flash EEPROM in the MC68HC912B32 in single-chip mode? In expanded mode? $8000-$FFFF single-chip mode and $0000-$7FFF (although disabled) in expanded-modes. What are the three methods that can erase EEPROM? Byte erase, row erase, bulk erase. How does the M68HC12 generate the 19 volts needed to program the EEPROM? A charge pump is used to generate the EEPROM programming voltage. The 37
program turns the charge pump on and then must wait at least 10 ms for the programming to be completed.
SOLUTIONS TO CHAPTER 10 PROBLEMS 10.1
What is wrong with the following code to get the 16-bit value of the TCNT register? LDAA $84 LDAB $85
10.2
If the TCNT register is incrementing at each M-clock cycle, the low byte will have changed during the time the high byte is being read. What is wrong with the following code to get the 16-bit value of the TCNT register? LDAB $85 LDAA $84
10.3
10.4 10.5
10.6 10.7 10.8 10.9
Get the high byte Get the low byte
Get the low byte Get the high byte
If the TCNT register is incrementing at each M-clock cycle, by the time you get through reading the low byte, it may have overflowed, causing the high byte to be incremented by one. How should you read the 16-bit TCNT value? LDD $84 Latches the 16-bit data from the TCNT register so the value is stable. How is the TCNT clock prescaler programmed? Bits PR2, PR1 and PR0 in the TMSK2 register may be set by the programmer. Give the name of the bit, the name of the register that it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit indicates that the timer has overflowed? Timer overflow flag, TOF, in the TFLG2 register at $8F, bit-7; the reset state is 0. b. What bit enables the timer overflow interrupts? TOI in the TMSK2 register at $8D, bit-7. The default state is interrupts disabled. c. What bits are used to prescale the timer clock? PR2, PR1 and PR0, in the TMSK2 register at $8D, bits 2, 1 and 0. The default state is 000 to divide by 1. When is the timer overflow flag set? When the TCNT register rolls over from $FFFF to $0000. How is the timer overflow flag reset? By the software writing a one to bit-7 of TFLG2 register. What timing resolution can be achieved with the output compare? 1 M-clock cycle times the prescaler value in TMSK2. Give the name of the bit, the name of the register that it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit indicates that a comparison has been made on Output Compare 2? C2F, in the TFLG1 register at $8E, bit 2. The reset state is 0. b. What bit enables the Output Compare 2 interrupt? C2I, in the TMSK1 register at $8C, bit 2. The reset state is interrupts disabled. c. What bits are used to set the Output Compare 3 I/O pin high on a successful comparison? OM3 and OL3 in the TCTL2 register at $89, bits 7 and 6. The reset state is for the timer to be disconnected from the output pin. 38
10.10
Write a small section of code to set the Output Compare 2 I/O pin to toggle on every comparison. ldaa staa
10.11
10.13
10.14
10.17
#%00000010 $8C
; C1I position ;Write to TMSK1
$14,#%00000101 $14,#%00000010 $15,#%10000000
bset
$14,#%10000000
; ; ; ; ; ;
Set RTR2, RTR0 in RTICTL Clear RTR1 in RTICTL Write to RTIFLG to reset real time interrupt flag Write to RTICTL to enable real time interrupts
Write a short section of code demonstrating how to reset the COP timer. #$55 $17 #$AA $17
; ; ; ;
Arm pattern Write to COPRST register Reset pattern Write to COPRST register
Write a short section of code demonstrating how to enable the Pulse Accumulator as an event counter counting rising edges. $A0,#%01010000 $A0,#%00100000
; Set PAEN and PEDGE in PACTL ; Clear PAMOD in PACTL
Write a short section of code demonstrating how to enable the Pulse Accumulator as a gated time accumulator with a high level enable accumulation. bset bclr
10.20
; C2F position ; Write to TFLG1
bset bclr bset
bset bclr
10.19
#%00000100 $8E
Write a short section of code demonstrating how to enable the real time interrupt and to set the nominal rate to 16.384 ms assuming a 8 MHz M-clock.
ldaa staa ldaa staa
10.18
; Set bits 7,6,5 high ; Write the Output Compare data register OC7D ; Enable bits 7, 6, and 5 in OC7M mask reg
Write a short section of code demonstrating how to enable the Input Capture 1 interrupts. ldaa staa
10.16
#%11100000 $83 $82
What two registers control which data bits are output when the Output Compare 7 flag is set? The Output Compare 7 Data (OC7D) register located at $83 and the Output Compare 7 Mask (OC7M) register located at $82. How does the programmer select the active edge for Input Capture 2? Timer Control Register 4 (TCTL4) at $8B contains bits to select the edge used for the input capture. Bits 5 and 4 control the edge for IC2 by the following truth table: EDG2B EDG2A Edge 0 0 Capture Disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge, rising or falling Write a short section of code demonstrating how to reset the Input Capture 2 Flag C2F. ldaa staa
10.15
; Set OM2, OL2 to 01 ; Write to TCTL2 register
Write a small section of code to enable Output Compare 1 to set bits PT7, PT6 and PT5 to one on the next successful comparison. ldaa staa staa
10.12
#%00010000 $89
$A0,x $A0,x
%01100000 ; Set PAEN and PAMOD in PACTL %00010000 ; Clear PEDGE in PACTL
What bit in what register must be set to enable the Pulse Accumulator Input Edge interrupt? PAI, bit-0 in PACTL, $A0 must be set.
39
SOLUTIONS TO CHAPTER 11 PROBLEMS 11.1
11.2
11.3 11.4
11.5
11.6
For the SCI0, give the name of the bit, the name of the register it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit enables the SCI0 transmitter? TE, in the SC0CR2 register at $C3, bit-3; the transmitter is disabled on reset. b. What bit enables the SCI0 receiver? RE, in the SC0CR2 register at $C3, bit-2; the receiver is disabled on reset. c. What bit determines how many data bits are sent? M (mode), in SC0CR1 at $C2, bit-4; the default is 1 start, 8 data and 1 stop bit. d. What bit can the user test to see if the last character has cleared the transmit data buffer? TDRE, in the SC0SR1 at $C4, bit-7; the default is that the buffer is empty. e. What bit can the user test to see if a new character has been received? RDRF, in the SC0SR1 at $C4, bit-5; the default is that the register is not full. f. What bit is used to indicate the software is not reading data from the SC0DRL fast enough? OR, in SC0SR1 at $C4, bit-3; no overrun by default. g. What bit is an indication that the communication channel is noisy? NF, in SC0SR1 at $C4, bit-2; default is no noise. h. What bit is an indication that the sending and receiving baud rates may not be identical? FE, in SC0SR1 at $C4, bit-1; default to no framing error. For the SCI0, give the name of the bit, the name of the register it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit enables an interrupt when the transmit buffer is empty? TIE, in the SC0CR2 register at $C3, bit-7; TDRE interrupts are disabled. b. What bit enables an interrupt when the transmitter has completely emptied its serial shift register? TCIE, in the SC0CR2 at $C3, bit-6; transmit complete interrupts are disabled. c. What bit enables interrupts by the SCI0 receiver? RIE, in the SC0CR2 at $C3, bit-5; receiver interrupts are disabled. What SCI0 receiver conditions can generate an interrupt? Receive data register full, receiver overrun, idle line detect. What different status information do the SCI0 status bits TDRE and TC give? TDRE indicates that the last character has been transferred from the SC0DRL transmit register to the output shift register. TC, transmission complete, indicates that the last character has been shifted out of the shift register. Give the meanings of the following mnemonics. TDRE - Transmit Data Register Empty TC - Transmission Complete RDRF - Receive Data Register Full OR - (Receiver) OverRun FE - Framing Error What is the M68HC12 I/O address for the SC0BDH register? $C0
40
11.7 11.8 11.9
11.10
11.11
11.12
11.13
What is the value used to initialize the SCI0 for 4800 baud assuming an E-clock = 8.0 MHz? 10410 Which port and which bits are the serial communications interface (SCI0) transmitted and received data? Port S, Pins 1 (TxD) and 0 (RxD) For the SPI, give the name of the bit, the name of the register it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit enables the SPI? SPE, in the SP0CR1 register at $D0, bit-6; the default state is SPI disabled. b. What bit selects the master or slave mode? MSTR, in the SP0CR1 register at $D0, bit-4; SPI configured as a slave. c. What bits select the data transfer rate? SPR2, SPR1, SPR0, in the SP0BR register at $D2, bit-2, -1, -0; the reset state is 000. d. What bit is the Master Output/Slave Input? MOSI, Port S, $D6, bit-5; the default is to act as Port S, bit-5. e. What bit is the Master Input/Slave Output? MISO, Port S, $D6, bit-4; the default is to act as Port S, bit-4. For the SPI, give the name of the bit, the name of the register it is in, the register's address, which bit, and the default or reset state of the bit for each of the following: a. What bit indicates the SPI has completely sent the last data? SPIF, SP0SR at $D3, bit-7; default state is reset. b. What bit indicates an error has occurred when new data has been written to the output register before the old data has cleared? WCOL, SP0SR at $D3, bit-6; default is reset. c. What bit is set to enable SPI interrupts? SPIE, SP0CR1 at $D0, bit-7; interrupts are disabled. How does the SPI differ from the SCI? The SPI is a synchronous serial port. Data bits are transferred from a master to a slave when the master generates a SCK signal. Data rates can be much higher with this system than with the SCI. How does a slave station SPI send data to the master station? The slave station shifts data to the master as the master is shift data to the slave. All data transfer is controlled by the master SCK signal. What do the following mnemonics mean in the operation of the SPI? & S& S - Slave select; SCK - SPI Clock; MOSI - Master Out, Slave In; MOMI Master Out, Master IN; MISO - Master In, Slave Out; SISO - Slave In, Slave Out; SPIE - SPI Interrupt Enable; SPE - SPI System Enable; MSTR - Master/slave Mode Select
SOLUTIONS TO CHAPTER 12 PROBLEMS 12-1 12-2 12-3
How is the A/D powered up? By writing a 1 to the ADPU bit in the ATDCTL2 register. How long must the program delay before using the A/D after powering it up? At least 100 µs. The A/D is programmed to convert a sequence of four channels in continuous conversion mode. What is the maximum frequency signal on PAD0 that can be 41
12-4
12-5
12-6
converted without aliasing (ignore aperture time effects, assume the final sample time is two ATD clocks and the ATD clock is 2 MHz). The conversion time for any one channel is 18 ATD clock periods giving the total sequence conversion time of 72 clocks = 36 µs. Thus the sampling frequency for any one channel is 27.78 kHz and the Nyquist frequency is 13.89 kHz. The analog input ranges from 1 volt to 4 volts. a. What should VRH and VRL be? VRH = 4V, VRL = 1 V. b. What is the resolution? 3 V/256 = 11.72 mV c. The analog result register shows $56. What is the analog voltage? $56 = 8610. The input voltage is 86*11.72 mV + VRL = 1.007 V + 1.000 V = 2.007 V. The analog input is 0 to 5 volts and VRH = 5, VRL = 0. The A/D reading is $24. What is the analog input voltage? $24 = 3610. The resolution is 5 V/256 = 19.5 mV, therefore the input voltage is 36*19.5 mV = 0.70 V. The following bytes are written to the ATDCTL to initiate the conversion. Give the channels expected in the A/D result registers ADR0H - ADR7H. Byte ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 00000000 PAD0 PAD0 PAD0 PAD0 ------------00000100 PAD4 PAD4 PAD4 PAD4 ------------00010000 PAD0 PAD1 PAD2 PAD3 ------------00010100 PAD4 PAD5 PAD6 PAD7 ------------01010000 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 01001100 VRH VRH VRH VRH VRH VRH VRH VRH
SOLUTIONS TO CHAPTER 13 PROBLEMS 13-1
13-2
13-3
Using table-lookup (instead of a fuzzy logic system), how many bytes would be needed for the table in a system with three inputs with 8-bit resolution on each input and one output with 8-bits resolution? 256 x 256 x 256 = 16,777,216 Referring to Figure 13-4, for what temperature or temperatures are the expressions 'temperature is cold' and 'temperature is warm' true to the same degree? $78 to $88 Sketch graphical representations of the following input membership functions... a) LOW FCB $20,$60,$08,$10 ;pt1,pt2,slope1,slope2 b) MID FCB $60,$A0,$10,$0B ;pt1,pt2,slope1,slope2 c) HI FCB $A0,$E0,$0B,$08 ;pt1,pt2,slope1,slope2
42
Problem 13-3. 13-4
13-5
13-6
13-7
What is the maximum number of rules that would be needed in a fuzzy logic system that has three inputs with three labels each? How many fuzzy inputs would there be in such a system and how many bytes of RAM would that require? There are a maximum of 3 x 3 x 3 = 27 rules. Each of the three inputs has three labels so there are nine fuzzy inputs and these require nine bytes of storage. For the fuzzy logic system in Example 13-4, how many bytes of memory in the knowledge base did it take for all 25 rules? There are five bytes for each rule plus the Rule_end separator = 126 bytes. In Figure 13-9, how many rules would be active if temperature was $C0 and pressure was $90? Which rule(s) would be active? Four rules are active; [19], [20], [24], [25] Using Figure 13-11, what value should be in FanSpeed if temperature is $B0 and pressure is $38? $58 43
13-8
Manually perform the defuzzification computation for the system in Example 13-4 if the temperature is $60 and pressure is $20. Using Figure 13-8, the fuzzified inputs are: Cold = 0, Cool = $FF, Normal = 00, Warm = 00, Hot = 00 VeryLo = $80, Low = $80, Med = 00, High = 00, VeryHi = 00 Using a rule matrix like Table 13-3 we can complete a rule evaluation table like Table 13-4:
Rule evaluation Fuzzy Input #1
Fuzzy Input #2
Min(#1:#2)
Current Fuzzy Output
New Fuzzy Output Max(Min:Current)
1 2 3 4 5
Cold=$00 Cold=$00 Cold=$00 Cold=$00 Cold=$00
VeryLo=$80 Low=$80 Medium=$00 High=$00 VeryHi=$00
$00 $00 $00 $00 $00
Stop=$00 Stop=$00 Stop=$00 Stop=$00 Stop=$00
Stop=$00 Stop=$00 Stop=$00 Stop=$00 Stop=$00
6 7 8 9 10
Cool=$FF Cool=$FF Cool=$FF Cool=$FF Cool=$FF
VeryLo=$80 Low=$80 Medium=$00 High=$00 VeryHi=$00
$80 $80 $00 $00 $00
Stop=$00 Stop=$80 Slow=$00 Slow=$00 Slow=$00
Stop=$80 Stop=$80 Slow=$00 Slow=$00 Slow=$00
11 12 13 14 15
Normal=$00 Normal=$00 Normal=$00 Normal=$00 Normal=$00
VeryLo=$80 Low=$80 Medium=$00 High=$00 VeryHi=$00
$00 $00 $00 $00 $00
Slow=$00 Slow=$00 Mid=$00 Mid=$00 Mid=$00
Slow=$00 Slow=$00 Mid=$00 Mid=$00 Mid=$00
16 17 18 19 20
Warm=$00 Warm=$00 Warm=$00 Warm=$00 Warm=$00
VeryLo=$80 Low=$80 Medium=$00 High=$00 VeryHi=$00
$00 $00 $00 $00 $00
Slow=$00 Mid=$00 Fast=$00 Fast=$00 Fast=$00
Slow=$00 Mid=$00 Fast=$00 Fast=$00 Fast=$00
21 22 23 24 25
Hot=$00 Hot=$00 Hot=$00 Hot=$00 Hot=$00
VeryLo=$80 Low=$80 Medium=$00 High=$00 VeryHi=$00
$00 $00 $00 $00 $00
Mid=$00 Fast=$00 Fast=$00 FullOn=$00 FullOn=$00
Mid=$00 Fast=$00 Fast=$00 FullOn=$00 FullOn=$00
Rule
From this we see the fuzzy outputs are: Stop = $80, Slow = 00, Mid = 00, Fast = 00, FullOn = 00 Using Figure 13-10 and equation (13.1) we calculate: $00($80%$00($00%$00($00%$00($00%$00($00 $80%$00%$00%$00%$00 $00 Fan Speed' '$00 $80 Fan Speed'
44
13-9
This can be checked by using Figure 13-11. How many bytes of program space are used for the executable portion of the fuzzy logic program in Example 13-4? !52
SOLUTIONS TO CHAPTER 14 PROBLEMS
Problem 14-1.
14-1
14-2
14-3
This is the waveform for one bit time in a BDM communication. Which direction is data being transferred (host-to-target or target-to-host)? From the target HC12 to the host pod. Looking at the waveform in problem 14-1, what causes the portion of the waveform labeled [1]? The portion labeled [2]? [1] is a slow RC rise because neither the host nor the pod is driving the BKGD pin at this time. [2] is the fast rising edge caused by the target-driven speedup pulse. This is the waveform for a BDM command. What is the command?
Problem 14-3.
from address $FF01. The data is $C0 (low half of $E4C0) Looking at the waveform in problem 14-3, what is the portion labeled [3] for? This delay allows the target BDM to find a free bus cycle and complete the read so the host pod can read the data from the target HC12. Draw an approximate waveform for a BDM command to write $81 to address $08F1. READ_BD_BYTE
14-4
14-5
45
Problem 14-5. 14-6
14-7
14-8
Where are each of the user registers CCR, D, X, Y, SP, and PC saved while the background debug mode is active? CCR is saved in the BDM register CCRSAV at $FF06 in the BDM map, D is saved in CPU temporary register TMP3, X, Y, and SP are not explicitly saved but they do not change because the BDM firmware avoids using these registers, PC is saved in CPU temporary register TMP2. Suppose a target application system is connected to a BDM pod. Which of the following types of memory could be programmed using the BDM interface? a) an external 256 Kbyte RAM (in an MC68HC812A4 based system) b) 32 Kbyte on-chip flash EEPROM (in an MC68HC912B32 based system) c) on-chip EEPROM d) all of the above e) b and c d) All of the above. BDM can see any memory locations the CPU can see. The following state information was captured in an MC68HC12 system. ************************************** Label> ADDR DATA && L& S& T& RB R&/ W
Base > Hex Hex Binary Binary 001 0801 55AA 1 0 ************************************** What took place during this cycle? && L& S& T& RB:R/W:A0 = 1:0:1 (RW-TYP = WLH) This is a misaligned write of $AA55 to address $0801 in the on-chip RAM. Use the following logic analyzer state listing to answer questions 14-9 through 14-14. ************************************** Label> ADDR DATA RW_TYP PER PEF Base > Hex Hex Symbol Symbol Symbol 1 0822 2 7E09 3 0824 4____0826 5 0901 6 7698 7____0828 8____082A 9 0800 10 082C 11____082E
7E09 7E09 01C6 64FD 7698 7698 0800 7D19 8602 01CE 6000
R16 ALL sev ????/???? ????/???? ????/???? R8L LAT sod 0822/7E09 ????/???? ????/???? R16 ALL ????/???? 0822/7E09 ????/???? R16______ALD____sev__????/???? 0824/01C6 0822/7E09 WLH W LAT 0822 7E0901 STX $0901 R8H O-f (write $9876 to $0901) R16_P____ALL____sod__ R16_P____ALD____sod__0825 C664 LDAB #$64 (100) R16 R ALD 0827 FD0800 LDY $0800 R16 O-P (read $8602 from $0800) R16_P____ALD sev__
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12 1901 1986 W8L Wh LAT 082A 7D1901 STY $1901 13 1902 0202 W8H Wl (write $8602 to $1901,1902) 14 0202 0202 R8H O-f 15____0830 CD61 R16_P____ALL____int__ 16 FFEC FF4E R16 V ALD Begin processing interrupt 17 09FE 082D W16 S LAT (vector $FF4E fetched from $FFEC) 18 FF4E 05FB R16 P (this is the Timer Ch.1 vector) 19 09FC 8602 W16 S ALD 20 09FA 9876 W16 S 21 FF50 F89A R16 P 22 09F8 6402 W16 S ALD 23 09F7 0988 W8L s 24____FF52 05FB R16_P___________sev__ **************************************
14-9
14-10 14-11
14-12
14-13
14-14 14-15 14-16
Beginning from state 001, reconstruct the internal pipe activity until you reach the start of an identifiable instruction. What is the address, opcode, and disassembled instruction? Address=$0822, opcode=$7E, instruction= STX $0901 Which state numbers correspond to the execution of the disassembled instruction? States 5, 6, and 7 There is a STY $1901 instruction in states 12-15. The instruction set documentation says this instruction should take 3 cycles. Why did it take 4 cycles? The write was a misaligned write to an external address so it had to be split into two adjacent 8-bit writes. Which state corresponds to a misaligned write to the on-chip RAM? What value was written, and to what address? State 5, $9876 was written to $0901. The WLH mnemonic tells you it was a misaligned write to on-chip RAM, or you could have disassembled the instruction and noted that $901 is an odd address in the on-chip RAM. An interrupt is serviced after state 15, what caused this interrupt? The interrupt was caused by timer channel 1 because the vector address was $FFEC Find an O-f cycle and an O-P cycle in the state listing. States 6 and 14 are O-f cycles, state 10 is an O-P cycle How is the tagging function enabled in the MC68HC12? By the serial BDM command TAG_GO. Which tagging mode would you set, using a BDM debug pod, for the following situations? State the 3-bit value you would write to BKEN1:BKEN0:BKPM for each case. a) To break on any write to address $0945 or $0946 b) To break just before executing the instruction at $0822 c) To repair a program error at $8110 in on-chip ROM d) To break if the value $55 is written to port T a) Dual address BDM (int) BKEN1:BKEN0:BKPM = 1:1:0 There are two addresses so a dual address mode is needed. R/W is needed in the breakpoint specification so the tagging mechanism can’t be used. b) Dual address BDM (tag) BKEN1:BKEN0:BKPM = 1:1:1 The tagging mechanism is needed since you want to break just before an instruction. Dual address BDM is called for because the problem statement said you have a BDM 47
14-17
14-18
14-19
14-20
debug pod connected which implies you are doing debug through BDM. c) Dual address SWI (tag) BKEN1:BKEN0:BKPM = 0:1:x You don’t want a mode that takes you to active background when you are doing program patches. d) Full address/data breakpoint (int) BKEN1:BKEN0:BKPM = 1:0:x This is the only mode that allows you to match a data value. What value would you write to BRKCT0:BRKCT1 to establish a breakpoint for a write of $80 to PORTB (address $0001)? BKCTL0:BKCTL1 = $8052 Which breakpoint type(s) require a valid user stack? a) SWI-based software breakpoints b) BGND-based software breakpoints c) Hardware breakpoints d) All of the above e) None of the above a) Of the types listed, only the SWI-based software breakpoint requires a valid user stack. What values would be written to all six registers in the breakpoint module to establish breakpoints for the instructions at $820 and $843? BKCTL0:BKCTL1 = $EC40 or: BKCTL0:BKCTL1 = $EC40 BRKDH:BRKDL = $0843 BRKDH:BRKDL = $0820 BRKAH:BRKAL = $0820 BRKAH:BRKAL = $0843 What is the breakpoint condition that is set by writing the following values to the breakpoint registers? BRKCT0 = $80 BRKCT1 = $72 BRKAH = $09 BRKAL = $FE BRKDH = $34 BRKDL = $12 Full address/data breakpoint (int); compare all 16 bits of data, R/W=0 (write); data to match is $3412; address to match is $09FE. Break at the next instruction boundary after a write of $3421 to address $09FE. Copyright 2000 Oxford University Press
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