SIMULATION, FABRICATION A N D CHARACTERIZATION Of PMOS TSASSISTOg DEVICE
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KOLEJ UNIVERSITI TEKNOLOGI TUN HUSSEIN ONN
PENGESAHAN STATUS LAPORAN PROJEK SARJANA TITLE: SIMULATION, FABRICATION AND CHARACTERIZATION OF PMOS TRANSISTOR DEVICE
SESI PENGAJIAN : 2006/2007 Saya S I T I I D Z U R A B I N T I Y U S U F mengaku membenarkan Laporan Projek Saijana ini disimpan di Perpustakaan dengan syarat-syarat kegunaan seperti berikut:
2. 3.
Laporan Projek Saijana adalah hakmilik Kolej Universiti Teknologi Tun Hussein Onn. Perpustakaan dibenarkan membuat salinan untuk tujuan pengajian sahaja. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. ** Sila tandakan (V) SULIT
TERHAD
(Mengandungi maklumat y a n g berdaijah keselamatan atau kepentingan Malaysia seperti y a n g termaktub di dalam A K T A R A H S I A R A S M I 1972) (Mengandungi maklumat T E R H A D yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan
TIDAK TERHAD Disahkan oleh
(TANDATANGAN PENULIS)
(TANDATANGAN PENYELIA)
Alamat Tetap: PEJABAT LADANG FELDA LEPAR U T A R A 13, W A K I L POS L E P A R U T A R A 1, 84300 B A N D A R P U S A T J E N G K A , PAHANG Tarikh:
21 D I S E M B E R 2006
P R O F . Dr. H A S H I M BIN SAIM N a m a Penyelia Tarikh:
21 D I S E M B E R 2006
CATATAN: **
Jika Laporan Projek Sarjana ini SULIT atau T E R H A D , sila lampirkan surat daripada pihak berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh laporan ini perlu di kelaskan sebagai S U L I T atau TERHAD.
"I hereby declare that I have read this thesis and in my opinion this thesis in terms of content and quality requirement fulfills the purpose for the award of the Master of Electrical Engineering"
Signature
Name of Supervisor
: PROFESSOR Dr. HASHIM BIN SAIM
Date
: 21 DECEMBER 2006
SIMULATION, FABRICATION AND CHARACTERIZATION OF PMOS TRANSISTOR DEVICE
SITIIDZURA BINTI YUSUF
This thesis is submitted in partial to fulfillment of the requirement for the Master of Electrical Engineering
Faculty of Electrical And Electronic Engineering Tun Hussien Onn University College of Technology
DECEMBER, 2006
ii
" I hereby declare that the work in this thesis in my own except for quotations and summaries which have been duly acknowledged"
Signature Name of Student Date
P:
O)
tj SITI IDZURA BINTI YUSUF : 21 DECEMBER 2006
iii
Khas b u a t trunang M u h a m m a d Syukur Bin Ismail Setiap kejayaanku milik kita bersama
iv
ACKNOWLEDGEMENTS
I w o u l d like to e x p r e s s m y d e e p g r a t i t u d e e s p e c i a l l y to m y p r o j e c t s u p e r v i s o r , P r o f . D r . H a s h i m B. S a i m f o r the o p p u r t u n i t y a n d e n c o u r a g e m e n t g i v e n t h r o u g h o u t the entire p r o c e s s of m y p r o j e c t . I a m d e e p l y i n d e b t e d f o r his a d v i c e s a n d b y p r o v i d i n g the l a b o r a t o r y facility to m e a l o n g the w a y .
B e s i d e that, m y special t h a n k s to m y f a t h e r Y u s u f B H a m d a n , m y m o t h e r Z a i n o n Bt K a s r a n a n d m y s i b l i n g s w h o h a v e a l w a y s b e h i n d m e to s u p p o r t d u r i n g critical time. Y o u are a l w a y s in m y heart.
N o t f o r g e t i n g , to all m y S a i j a n a M E E m e m b e r s w h o h a v e h e l p e d m e a l o n g the w a y . T h a n k y o u f o r the s u g g e s t i o n s a n d e n c o u r a g e m e n t s .
cdliii
ABSTRACT
In a l o w s u p p l y v o l t a g e C M O S t e c h n o l o g y , it is d e s i r a b l e to s c a l e t h r e s h o l d v o l t a g e a n d g a t e l e n g t h f o r i m p r o v i n g circuit p e r f o r m a n c e . T h e r e f o r e , a p r o j e c t h a s b e e n carried out inside K U i T T H O ' s microelectronic c l e a n r o o m to p r o d u c e a m e t h o d that has better low p o w e r / l o w voltage current concentrate on p-channel ( P M O S ) . A n experiment w a s a l s o d o n e to d e t e r m i n e t h e r i g h t p a r a m e t e r v a l u e to b e u s e d f o r f a b r i c a t i o n p r o c e s s s u c h as o x i d a t i o n p r o c e s s t h i c k n e s s rate, s h e e t r e s i s t a n c e a n d m e t a l t h i c k n e s s . F r o m t h e p a r a m e t e r v a l u e o b t a i n e d , 0.3 m m a n d 0.5 m m P M O S t r a n s i s t o r h a d b e e n s u c c e s s f u l l y p r o d u c e d . F a b r i c a t i o n s i m u l a t i o n w a s p e r f o r m e d t o p r o d u c e a 0 . 1 |am a n d 0.3p.m P M O S transistor by using the I S E - T C A D software. T h e trade off between threshold voltage (VTH), g a t e l e n g t h (LG) a n d thin o x i d e t h i c k n e s s (t o x ) a r e d i s c u s s e d to d e t e r m i n e t h e c h a r a c t e r i s t i c s o f t h e t r a n s i s t o r s . It s h o w s t h a t f o r 0 . 3 m m (toX = 8 6 0 A ) P M O S t r a n s i s t o r t h e v a l u e o f V T H = - 3 . 3 3 V a n d 0.5 m m ( t ^ = 9 1 0 A ) , V T H v a l u e = - 4 . 3 V . F r o m t h e s i m u l a t i o n r e s u l t s h o w f o r 0.1 j i m (to* = 2 0 0 A ) , V T H = - 0 . 3 1 4 V a n d f o r 0 . 5 | i m ( 4 0 0 A ) V t h = - 0 . 6 3 4 V . T h e r e s u l t s h o w s that, w i t h d e c r e a s i n g g a t e l e n g t h a n d o x i d e t h i c k n e s s will p r o d u c e l o w e r v a l u e o f t h r e s h o l d v o l t a g e . M i n i m u m v a l u e o f t h r e s h o l d v o l t a g e c a n r e s u l t in a b e t t e r p e r f o r m a n c e o f t r a n s i s t o r . A n o t h e r p a r a m e t e r m u s t b e t a k e n into c o n s i d e r a t i o n s u c h as l e a k a g e c u r r e n t , r e s i s t i v i t y a n d c o n d u c t i v i t y to g e t a b e t t e r d e s i g n o f P M O S t r a n s i s t o r in f u t u r e r e s e a r c h .
cdliv
ABSTRAK
Untuk menghasilkan sumber voltan yang rendah dalam C M O S teknologi, p e n s k a l a a n v o l t a n a m b a n g , V T H d a n l e b a r g a t e , LQ u n t u k m e n g h a s i l k a n litar y a n g b e r k e u p a y a a n t i n g g i , m e r u p a k a n i s u e y a n g s a n g a t p e n t i n g . O l e h itu, p r o j e k ini telah d i j a l a n k a n di d a l a m m a k m a l m i k r o e l e k t r o n i k b i l i k b e r s i h K U i T T H O u n t u k m e n g h a s i l k a n resepi bagi P M O S transistor d e n g a n saiz y a n g m i n i m u m dan berprestasi t i n g g i . E k s p e r i m e n j u g a telah d i j a l a n k a n u n t u k m e n e n t u k a n nilai p a r a m e t e r y a n g s e s u a i u n t u k d i g u n a k a n d a l a m p r o s e s f a b r i k a s i iaitu p r o s e s p e n g o k s i d a a n u n t u k m e n c a r i k a d a r k e t e b a l a n o k s i d a get, r i n t a n g a n k e p i n g d a n k e t e b a l a n m e t a l . D a r i p a d a n i l a i p a r a m e t e r yang diperolehi, 0 . 3 m m dan 0 . 5 m m P M O S transistor telah b e r j a y a dihasilkan.
Fabrikasi
s e c a r a s i m u l a s i j u g a t e l a h d i j a l a n k a n u n t u k m e n g h a s i l k a n 0.1 | i m a n d 0.3(am P M O S transistor dengan m e n g g u n a k a n perisian I S E - T C A D . Perubahan antara voltan ambang (VTH), l e b a r g a t e (LG) d a n k e t e b a l a n l a p i s a n o k s i d a (t o x ) t e l a h d i b i n c a n g k a n u n t u k m e n e t u k a n ciri-ciri b a g i P M O S t r a n s i s t o r t e r s e b u t . H a s i l d a p a t d a r i p a d a f a b r i k a s i s e b e n a r m e n u n j u k k a n u n t u k t r a n s i s t o r b e r s a i z 0 . 3 m m (to X = 8 6 0 A ) P M O S t r a n s i s t o r VTH = - 3 . 3 3 V d a n 0 . 5 m m ( t o X = 9 1 0 A ) , nilai V T H = - 4 . 3 V . D a p a t a n h a s i l s i m u l a s i m e n u n j u k k a n u n t u k 0.1 | i m (t<, x = 2 0 0 A ) , V T H = - 0 . 3 1 4 V d a n 0.5FRM (t o x = 4 0 0 A ) , nilai Vth
=
-0.634V. Daripada keputusan yang diperolehi m e n u n j u k k a n b a h a w a dengan
k e l e b a r a n g e t y a n g m i n i m a d a n k e t e b a l a n o k s i d a y a n g lebih n i p i s a k a n m e n g h a s i l k a n P M O S t r a n s i s t o r d e n g a n nilai v o l t a n a m b a n g y a n g l e b i h r e n d a h . N i l a i v o l t a n a m b a n g y a n g l e b i h r e n d a h a k a n m e m p e n g a r u h i k e u p a y a a n t r a n s i s t o r . P a r a m e t e r - p a r a m e t e r lain perlu diambil kira seperti arus bocor, kerintangan dan k e k o n d u k s i a n u n t u k menghasilkan P M O S transistor yang berprestasi tinggi untuk kajian akan datang.
Vll
TABLE OF CONTENT
CHAPTER
CHAPTER I
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENT
vii
LIST OF FIGURES
xi
LIST OF TABLES
xiii
LIST OF SYMBOLS / ABBREVIATION
xiv
INTRODUCTION
1.1
General
1
1.2
Problem Statement
2
1.3
Project Objectives
3
1.4
Project Scope
3
1.5
Project Flow
4
viii CHAPTER II
LITERATURE REVIEW
2.1
Introduction
5
2.2
The M O S Transistor
5
2.3
P-Channel M O S F E T (PMOS)
6
2.3.1
2.4
Structure of P-Channel M O S ( P M O S )
Transistor
6
Qualitatitive I-V Behavior of P M O S
7
Transistor 2.5
C h a r a c t e r i s t i c s of the P M O S T r a n s i s t o r
2.6
Relationship between Gate Length, Threshold
2.7
2.8
2.9
9
Voltage and Gate Oxide Thickness
13
2.6.1
Gate Length
13
2.6.2
Gate Oxide Thickness
14
2.6.3
Threshold Voltage
15
Fabrication Process
15
2.7.1
Cleanroom Cleanliness
16
2.7.2
Cleaning Process
17
2.7.3
Oxidation Process
18
2.7.3.1 H o r i z o n t a l T u b e F u r n a c e
19
2.7.3.2 D r y O x y g e n
20
2.7.3.3 Water V a p o r Source
21
2.7.4
Diffusion
22
2.7.5
Photolithography
23
2.7.6
Metallization
24
Simulation Fabrication Process
25
2.8.1
Strongly Varying Length Scale
26
2.8.2
H i g h P e r f o r m a n c e in K e y O p e r a t i o n s
27
2.8.3
Stability
27
Previous Research
28
cdlvii
CHAPTER III
CHAPTER IV
METHODOLOGY
3.1
Introduction
30
3.2
M a s k Design and Creation
31
3.3
Fabrication Process M o d u l e
33
3.3.1
Drain and source regions
33
3.3.2
Gate Oxide Grown
35
3.3.3
Define Contact Hole
36
3.3.4
Aluminium Film Deposited
37
3.4
P M O S Characteristics and P e r f o r m a n c e
38
3.5
Simulation Fabrication Process
38
RESULTS AND DISCUSSION
4.1
Introduction
40
4.2
Recipes of P M O S F E T Devices
40
4.2.1
Process Parameter
41
4.2.1.1 O x i d a t i o n P r o c e s s
41
4.2.1.2 Diffusion
45
4.2.1.2.1 Sheet Resistance
4.2.2 4.3
4.4
45
4.2.1.3 M e t a l l i z a t i o n S h e e t R e s i s t a n c e
48
Fabrication Process
51
P M O S Characteristics Analysis
57
4.3.1
Simulation Fabrication Result
58
4.3.1.1 C o n c l u s i o n
64
4.3.2
Real Fabrication Result
65
4.3.3
Conclusion
71
P M O S Characteristics and P e r f o r m a n c e
72
CHAPTER V
CONCLUSION AND RECOMMENDATION
5.1
Introduction
74
5.2
Conclusion
74
5.3
Problems and Recommendation
77
5.3.1
U n i f o r m i t y in D i f f u s i o n P r o c e s s
77
5.3.2
M e a s u r e m e n t o f VTH V a l u e
77
5.3.3
Alignment
77
5.4
Suggestion for Future Research
REFERENCES
78
79
xi
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
1.1
The project flowchart
4
2.1
A n internal structure of p-channel M O S transistor
7
2.2
C r o s s s e c t i o n o f an e n h a n c e m e n t - m o d e P M O S t r a n s i s t o r
8
2 . 3 (a)
Vsg < Vth - cut off region
10
2.3(b)
Vsg ^ Vth - linear region
10
2.3(c)
P M O S w i t h c h a n n e l j u s t p i n c h o f f at t h e d r a i n
11
2.3(d)
P i n c h o f f f o r V S D > ( V S G + VTH) > 0
11
2.4
C l a s s 100 y e l l o w r o o m f o r p h o t o l i t h o g r a p h y p r o c e s s
16
2.5(a)
Cleaning Process Section
18
2.5(b)
D.I water
18
2.6
Furnace Equipment
20
2.7
Bubler water vapor source
21
2.8(a)
Spin on-dopant Equipment
24
2.8(b)
Transfer Patern Equipment
24
2.9
Physical Vapor Deposition(PVD) Equipment
25
2.10
ISE T C A D product overview
27
3.1
P M O S transistor layout
31
3.2
M a s k i n g d r a w i n g s t e p s in T u r b o C A D 2 0 0 2
32
3.3
Modules of M O S F E T P M O S fabrication process
33
3.4
Gate Oxide Grown
35
xii 3.5
D e f i n e Contact H o l e
36
3.6
C o m p l e t i o n of P M O S transistor fabrication
37
4.1
O x i d a t i o n thickness versus time f o r w e t oxidation
43
4.2
O x i d a t i o n thickness versus time f o r dry oxidation
44
4.3
Five Point of m e a s u r e m e n t
44
4.4(a)
E x a m p l e of sheet resistance graph m e a s u r e d b y f o u r point p r o b e f o r w a f e r A at p o i n t 1
4.4(b)
47
E x a m p l e of sheet resistance g r a p h m e a s u r e d b y four point p r o b e f o r w a f e r B (b) at point 1
47
4.5
G r a p h A l u m i n i u m thickness with d i f f e r e n t size o f a l u m i n i u m
50
4.6(a)
I D - V D characteristics o f O . l u m P M O S , thin oxide 4 0 0 A
58
4.6(b)
T r a n s f e r charateristics of 0.1 jam P M O S , thin o x i d e 4 0 0 A
59
4.7(a)
I D - V D characteristics of 0 . 3 u m P M O S , thin oxide 4 0 0 A
60
4.7(b)
T r a n s f e r charateristics of 0.3 jam P M O S , thin oxide 4 0 0 A
60
4.8(a)
I D - V D characteristics of 0. l u m P M O S , thin o x i d e 2 0 0 A
62
4.8(b)
T r a n s f e r charateristics of 0.1 (am P M O S , thin oxide 2 0 0 A
62
4.9(a)
I D - V D characteristics o f 0 . 3 u m P M O S , thin o x i d e 2 0 0 A
63
4.9(b)
T r a n s f e r charateristics of 0.3 (im P M O S , thin oxide 2 0 0 A
64
4.10
I D - V D characteristics of 0.3 m m P M O S ; V D = - 6 V ;
thin oxide 91 OA 4.11
I D - V D characteristics of 0.5 m m P M O S ; V D = - 6 V ;
thin oxide 91 OA 4.12
67
I D - V D characteristics of 0.3 m m P M O S ; V D = - 6 V ;
thin oxide 860A 4.13
66
69
I D - V D characteristics of 0.5 m m P M O S ; V D = - 6 V ; thin oxide 8 6 0 A
69
X111
LIST OF TABLES
NO. TABLE
TITLE
PAGE
2.1
Cleanroom cleanliness measurement
17
3.1
Modules of M O S F E T ( P M O S S ) fabrication process
33
3.2
Equipment of device and process parameter
38
4.1(a)
Wet oxidation thickness of wafer 1
42
4.1(b)
W e t oxidation thickness of wafer 2
42
4.2
Oxidation thickness for dry oxidation
4.3
Sheet resistance value different wafer
46
4.4
Metal thickness with different size of a l u m i n i u m
50
4.5
T h e recipes of P M O S transistor
51
4.6
Simulation fabrication result
65
4.7
Real fabrication result
70
4.8
Relationship between different gate oxide and gate
4.9
43
length versus gate delay
73
Gate delay with load capacitance
73
xiv
LIST OF S Y M B O L S / A B B R E V A T I O N S
A
s y m b o l f o r 10" 1 0 cm or 10~8m
c
Capacitance
Cox
Oxide capacitance per unit area
D
Diffusion coefficient
I
Current
ID
Drain current
ID-VD
Drain Current versus Drain / source Voltage
k
Boltzmann's constant
L
Length
LQ
Gate Length
n
Electron density
NI
Intrinsic carrier density
N
Doping density
Na
Acceptor doping density
Nc
E f f e c t i v e d e n s i t y o f states in t h e c o n d u c t i o n b a n d
Nd
Donor doping density
R
Resistance
Rs
Sheet Resistance
Si
Silicon
t
Thickness
tox
Oxide thickness
T
Temperature
V
Velocity
VD
Drain voltage
Vds
V o l t a g e gate to s o u r c e
Vb
Body voltage
Vg
Gate voltage
VGS
V o l t a g e gate to s o u r c e
VTH
Threshold voltage
W
Width
xd
Depletion layer width
xj
Junction depth
XN
D e p l e t i o n layer w i d t h in a n n - t y p e s e m i c o n d u c t o r
Mp
Hole mobility
CHAPTER I
INTRODUCTION
1.1
General
T h e M O S F E T circuit t e c h n o l o g y h a s d r a m a t i c a l l y c h a n g e d o v e r the last three d e c a d e s . S t a r t i n g w i t h a t e n - m i c r o n P M O S p r o c e s s w i t h a n a l u m i n u m g a t e and a single m e t a l l i z a t i o n layer a r o u n d 1970, the t e c h n o l o g y h a s e v o l v e d into a t e n t h - m i c r o n selfa l i g n e d - g a t e C M O S p r o c e s s w i t h u p to f i v e m e t a l l i z a t i o n levels. T h e transition f r o m d o p a n t d i f f u s i o n to ion i m p l a n t a t i o n , f r o m t h e r m a l o x i d a t i o n to o x i d e d e p o s i t i o n , f r o m a m e t a l g a t e to a p o l y - s i l i c o n gate, f r o m w e t c h e m i c a l e t c h i n g to dry e t c h i n g a n d m o r e r e c e n t l y f r o m a l u m i n u m (with 2 % c o p p e r ) w i r i n g to c o p p e r w i r i n g h a s p r o v i d e d vastly s u p e r i o r a n a l o g a n d digital C M O S circuits. T h e c h o i c e a n d c e n t e r i n g of target transistor p a r a m e t e r s - m o d e l i n g (such as t h r e s h o l d v o l t a g e , g a t e length, g a t e o x i d e t h i c k n e s s , etc) f o r h i g h s p e e d l o w - p o w e r / l o w v o l t a g e C M O S t e c h n o l o g i e s is a c u r r e n t c o n c e r n (Chang, 2000)[7], If p r o p e r C M O S scaling r u l e s are utilized, h i g h s p e e d C M O S t e c h n o l o g i e s can b e a c h i e v e d e v e n in c o n j u n c t i o n w i t h r e d u c e d s u p p l y v o l t a g e r e q u i r e m e n t s . d y n a m i c p o w e r dissipation in C M O S inverter circuits is g i v e n b y
The
(1.1)
2 P =f- CL. V D
w h e r e f is o p e r a t i n g f r e q u e n c y , C l is the l o a d i n g c a p a c i t a n c e , a n d V D is the s u p p l y v o l t a g e . Clearly, r e d u c i n g the s u p p l y v o l t a g e is the s i m p l e s t a p p r o a c h in r e d u c i n g the d y n a m i c p o w e r c o n s u m p t i o n . T h e t i m e d e l a y , x D in a C M O S g a t e is a p p r o x i m a t e l y given by
C V
CL J G tox VD
ID
(VD ^TH)
(1.2)
w h e r e L g is the transistor gate l e n g t h , toX is the gate o x i d e t h i c k n e s s , I D d r a i n c u r r e n t and VTH is the M O S transistor t h r e s h o l d v o l t a g e . E q u a t i o n 1.2 d e m o n s t r a t e s the n e e d f o r r e d u c i n g the g a t e o x i d e t h i c k n e s s , the g a t e l e n g t h , a n d the t r a n s i s t o r t h r e s h o l d v o l t a g e in o r d e r to p r e s e r v e the h i g h - s p e e d in a r e d u c e d v o l t a g e s u p p l y t e c h n o l o g y .
1.2
Problem Statement
S i n c e the s e m i c o n d u c t o r i n d u s t r y g r o w t h r a p i d l y , c o m p e t i t i o n a m o n g c o m p a n i e s to fulfill m a r k e t d e m a n d s h a s b e c o m e i n c r e a s i n g l y intense. T h e r e f o r e , m a n y data a n d parameters obtained from researches were not published and kept confidential. Hence, e a c h f a b r i c a t i o n l a b o r a t o r i e s h a v e c r e a t e d t h e i r o w n t e c h n o l o g i e s . K U i T T H O as an e d u c a t i o n institution is also m a k i n g an e f f o r t to p r o d u c e a M O S F E T t e c h n o l o g y transistor w i t h the e q u i p m e n t p r o v i d e d in the K U i T T H O ' s M i c r o e l e c t r o n i c C l e a n r o o m . T h e r e f o r e , the p u r p o s e of this p r o j e c t w a s to b u i l d a first M O S F E T t e c h n o l o g y transistor, w h i c h w a s a i m e d f o r better l o w p o w e r / l o w v o l t a g e c u r r e n t c o n c e n t r a t e on p - c h a n n e l ( P M O S ) transistors.
3 1.3
Project Objectives
T h e o b j e c t i v e s o f this p r o j e c t are:
1.
T o produce a recipe of M O S F E T devices ( P M O S transistor).
2.
T o d e t e r m i n e t h e m i n i m u m m a s k d e s i g n that c a n b e f a b r i c a t e d in K U i T T H O ' s c l e a n r o o m to p r o d u c e t r a n s i s t o r w i t h m i n i m u m g a t e l e n g t h .
3.
T o d e t e r m i n e t r a n s i s t o r r e g i o n o p e r a t i o n w h i c h are v e r y i m p o r t a n t in l o w - v o l t a g e and l o w - p o w e r application f r o m the I V characteristics o f P M O S transistor.
4.
T o d e t e r m i n e t h e t r a d e - o f f b e t w e e n t h r e s h o l d v o l t a g e (VTH) a n d t h e m i n i m u m g a t e l e n g t h (LQ) f o r o p t i m i z i n g t h e p e r f o r m a n c e o f P M O S t r a n s i s t o r s f o r l o w v o l t a g e / l o w p o w e r h i g h - s p e e d d i g i t a l C M O S circuit.
1.4
Project Scope
1.
T h e p r o j e c t w a s d o n e w i t h t h e p r o c e s s e q u i p m e n t s in M i c r o e l c t r o n i c C l e a n r o o m at K U i T T H O . T h e d a t a t h a t w a s o b t a i n e d m i g h t b e d i f f e r e n t w i t h o t h e r c l e a n r o o m . It d e p e n d s o n t h e e q u i p m e n t c a p a b i l i t y a n d t h e c l a s s o f t h e c l e a n r o o m .
2.
T h e p r o j e c t c o n c e n t r a t e d o n P M O S t r a n s i s t o r d e v i c e , i n c l u d i n g the e f f e c t o f t h r e s h o l d v o l t a g e ( V T H ) t h i n o x i d e t h i c k n e s s (t o x ) a n d g a t e l e n g t h ( L G ) to ID-V D characteristics.
3.
T h e r e w e r e 4 s t e p s t h a t w e r e t a k e n in this p r o j e c t w h i c h w e r e : i.
E s t a b l i s h i n g p r o c e s s m o d u l e , p r o c e s s p a r a m e t e r s , p r o c e s s f l o w and process run card.
ii.
Optimizing and characterizing process module.
4 iii.
I n t e g r a t i n g the p r o c e s s m o d u l e a n d starting t h e f a b r i c a t i o n p r o c e s s o f M O S F E T ( P M O S ) device.
iv.
1.5
Analyzing and testing product.
Project Flow
F i g u r e 1.1: T h e p r o j e c t f l o w c h a r t
CHAPTER II
LITERATURE REVIEW
2.1
Introduction
T h i s c h a p t e r will h i g h l i g h t on the u n d e r s t a n d i n g o f t r a n s i s t o r d e v i c e m a i n l y M O S F E T ( M e t a l O x i d e S e m i c o n d u c t o r Field E f f e c t T r a n s i s t o r ) . T h i s p r o j e c t focuses on the f a b r i c a t i o n p r o c e s s of M O S F E T d e v i c e s . P r i o r to that, the c h a r a c t e r i s t i c s and p h y s i c a l structure o f P M O S t r a n s i s t o r w a s studied.
2.2
The MOS Transistor
T h e s e d e v i c e s are k n o w n as F E T ' s (Field e f f e c t transistors), w h i c h consist of three r e g i o n s ; s o u r c e , drain and gate. T h e r e s i s t a n c e p a t h b e t w e e n the drain and source is c o n t r o l l e d b y a p p l y i n g a v o l t a g e to the gate. T h i s v a r i e s the d e p l e t i o n layer u n d e r the gate a n d thus r e d u c e s or i n c r e a s e s the c o n d u c t a n c e path. T h e F E T input i m p e d a n c e (unlike the B J T w h i c h is a f e w k O ) is v e r y high ( ~ M H ' s ) and as a result the gate current can b e c o n s i d e r e d as zero.
